1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select ARM_ERRATA_855873 5 select FSL_LSCH2 6 select SYS_FSL_SRDS_1 7 select SYS_HAS_SERDES 8 select SYS_FSL_DDR_BE 9 select SYS_FSL_MMDC 10 select SYS_FSL_ERRATUM_A010315 11 select SYS_FSL_ERRATUM_A009798 12 select SYS_FSL_ERRATUM_A008997 13 select SYS_FSL_ERRATUM_A009007 14 select SYS_FSL_ERRATUM_A009008 15 select ARCH_EARLY_INIT_R 16 select BOARD_EARLY_INIT_F 17 imply PANIC_HANG 18 19config ARCH_LS1043A 20 bool 21 select ARMV8_SET_SMPEN 22 select ARM_ERRATA_855873 23 select FSL_LSCH2 24 select SYS_FSL_SRDS_1 25 select SYS_HAS_SERDES 26 select SYS_FSL_DDR 27 select SYS_FSL_DDR_BE 28 select SYS_FSL_DDR_VER_50 29 select SYS_FSL_ERRATUM_A008850 30 select SYS_FSL_ERRATUM_A008997 31 select SYS_FSL_ERRATUM_A009007 32 select SYS_FSL_ERRATUM_A009008 33 select SYS_FSL_ERRATUM_A009660 34 select SYS_FSL_ERRATUM_A009663 35 select SYS_FSL_ERRATUM_A009798 36 select SYS_FSL_ERRATUM_A009929 37 select SYS_FSL_ERRATUM_A009942 38 select SYS_FSL_ERRATUM_A010315 39 select SYS_FSL_ERRATUM_A010539 40 select SYS_FSL_HAS_DDR3 41 select SYS_FSL_HAS_DDR4 42 select ARCH_EARLY_INIT_R 43 select BOARD_EARLY_INIT_F 44 imply SCSI 45 imply SCSI_AHCI 46 imply CMD_PCI 47 48config ARCH_LS1046A 49 bool 50 select ARMV8_SET_SMPEN 51 select FSL_LSCH2 52 select SYS_FSL_SRDS_1 53 select SYS_HAS_SERDES 54 select SYS_FSL_DDR 55 select SYS_FSL_DDR_BE 56 select SYS_FSL_DDR_VER_50 57 select SYS_FSL_ERRATUM_A008336 58 select SYS_FSL_ERRATUM_A008511 59 select SYS_FSL_ERRATUM_A008850 60 select SYS_FSL_ERRATUM_A008997 61 select SYS_FSL_ERRATUM_A009007 62 select SYS_FSL_ERRATUM_A009008 63 select SYS_FSL_ERRATUM_A009798 64 select SYS_FSL_ERRATUM_A009801 65 select SYS_FSL_ERRATUM_A009803 66 select SYS_FSL_ERRATUM_A009942 67 select SYS_FSL_ERRATUM_A010165 68 select SYS_FSL_ERRATUM_A010539 69 select SYS_FSL_HAS_DDR4 70 select SYS_FSL_SRDS_2 71 select ARCH_EARLY_INIT_R 72 select BOARD_EARLY_INIT_F 73 imply SCSI 74 imply SCSI_AHCI 75 76config ARCH_LS1088A 77 bool 78 select ARMV8_SET_SMPEN 79 select ARM_ERRATA_855873 80 select FSL_LSCH3 81 select SYS_FSL_SRDS_1 82 select SYS_HAS_SERDES 83 select SYS_FSL_DDR 84 select SYS_FSL_DDR_LE 85 select SYS_FSL_DDR_VER_50 86 select SYS_FSL_EC1 87 select SYS_FSL_EC2 88 select SYS_FSL_ERRATUM_A009803 89 select SYS_FSL_ERRATUM_A009942 90 select SYS_FSL_ERRATUM_A010165 91 select SYS_FSL_ERRATUM_A008511 92 select SYS_FSL_ERRATUM_A008850 93 select SYS_FSL_ERRATUM_A009007 94 select SYS_FSL_HAS_CCI400 95 select SYS_FSL_HAS_DDR4 96 select SYS_FSL_HAS_RGMII 97 select SYS_FSL_HAS_SEC 98 select SYS_FSL_SEC_COMPAT_5 99 select SYS_FSL_SEC_LE 100 select SYS_FSL_SRDS_1 101 select SYS_FSL_SRDS_2 102 select FSL_TZASC_1 103 select ARCH_EARLY_INIT_R 104 select BOARD_EARLY_INIT_F 105 imply SCSI 106 imply PANIC_HANG 107 108config ARCH_LS2080A 109 bool 110 select ARMV8_SET_SMPEN 111 select ARM_ERRATA_826974 112 select ARM_ERRATA_828024 113 select ARM_ERRATA_829520 114 select ARM_ERRATA_833471 115 select FSL_LSCH3 116 select SYS_FSL_SRDS_1 117 select SYS_HAS_SERDES 118 select SYS_FSL_DDR 119 select SYS_FSL_DDR_LE 120 select SYS_FSL_DDR_VER_50 121 select SYS_FSL_HAS_CCN504 122 select SYS_FSL_HAS_DP_DDR 123 select SYS_FSL_HAS_SEC 124 select SYS_FSL_HAS_DDR4 125 select SYS_FSL_SEC_COMPAT_5 126 select SYS_FSL_SEC_LE 127 select SYS_FSL_SRDS_2 128 select FSL_TZASC_1 129 select FSL_TZASC_2 130 select SYS_FSL_ERRATUM_A008336 131 select SYS_FSL_ERRATUM_A008511 132 select SYS_FSL_ERRATUM_A008514 133 select SYS_FSL_ERRATUM_A008585 134 select SYS_FSL_ERRATUM_A008997 135 select SYS_FSL_ERRATUM_A009007 136 select SYS_FSL_ERRATUM_A009008 137 select SYS_FSL_ERRATUM_A009635 138 select SYS_FSL_ERRATUM_A009663 139 select SYS_FSL_ERRATUM_A009798 140 select SYS_FSL_ERRATUM_A009801 141 select SYS_FSL_ERRATUM_A009803 142 select SYS_FSL_ERRATUM_A009942 143 select SYS_FSL_ERRATUM_A010165 144 select SYS_FSL_ERRATUM_A009203 145 select ARCH_EARLY_INIT_R 146 select BOARD_EARLY_INIT_F 147 imply PANIC_HANG 148 149config FSL_LSCH2 150 bool 151 select SYS_FSL_HAS_CCI400 152 select SYS_FSL_HAS_SEC 153 select SYS_FSL_SEC_COMPAT_5 154 select SYS_FSL_SEC_BE 155 156config FSL_LSCH3 157 bool 158 159config FSL_MC_ENET 160 bool "Management Complex network" 161 depends on ARCH_LS2080A || ARCH_LS1088A 162 default y 163 select RESV_RAM 164 help 165 Enable Management Complex (MC) network 166 167menu "Layerscape architecture" 168 depends on FSL_LSCH2 || FSL_LSCH3 169 170config FSL_PCIE_COMPAT 171 string "PCIe compatible of Kernel DT" 172 depends on PCIE_LAYERSCAPE 173 default "fsl,ls1012a-pcie" if ARCH_LS1012A 174 default "fsl,ls1043a-pcie" if ARCH_LS1043A 175 default "fsl,ls1046a-pcie" if ARCH_LS1046A 176 default "fsl,ls2080a-pcie" if ARCH_LS2080A 177 default "fsl,ls1088a-pcie" if ARCH_LS1088A 178 help 179 This compatible is used to find pci controller node in Kernel DT 180 to complete fixup. 181 182config HAS_FEATURE_GIC64K_ALIGN 183 bool 184 default y if ARCH_LS1043A 185 186config HAS_FEATURE_ENHANCED_MSI 187 bool 188 default y if ARCH_LS1043A 189 190menu "Layerscape PPA" 191config FSL_LS_PPA 192 bool "FSL Layerscape PPA firmware support" 193 depends on !ARMV8_PSCI 194 select ARMV8_SEC_FIRMWARE_SUPPORT 195 select SEC_FIRMWARE_ARMV8_PSCI 196 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 197 help 198 The FSL Primary Protected Application (PPA) is a software component 199 which is loaded during boot stage, and then remains resident in RAM 200 and runs in the TrustZone after boot. 201 Say y to enable it. 202 203config SPL_FSL_LS_PPA 204 bool "FSL Layerscape PPA firmware support for SPL build" 205 depends on !ARMV8_PSCI 206 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 207 select SEC_FIRMWARE_ARMV8_PSCI 208 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 209 help 210 The FSL Primary Protected Application (PPA) is a software component 211 which is loaded during boot stage, and then remains resident in RAM 212 and runs in the TrustZone after boot. This is to load PPA during SPL 213 stage instead of the RAM version of U-Boot. Once PPA is initialized, 214 the rest of U-Boot (including RAM version) runs at EL2. 215choice 216 prompt "FSL Layerscape PPA firmware loading-media select" 217 depends on FSL_LS_PPA 218 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 219 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 220 default SYS_LS_PPA_FW_IN_XIP 221 222config SYS_LS_PPA_FW_IN_XIP 223 bool "XIP" 224 help 225 Say Y here if the PPA firmware locate at XIP flash, such 226 as NOR or QSPI flash. 227 228config SYS_LS_PPA_FW_IN_MMC 229 bool "eMMC or SD Card" 230 help 231 Say Y here if the PPA firmware locate at eMMC/SD card. 232 233config SYS_LS_PPA_FW_IN_NAND 234 bool "NAND" 235 help 236 Say Y here if the PPA firmware locate at NAND flash. 237 238endchoice 239 240config SYS_LS_PPA_FW_ADDR 241 hex "Address of PPA firmware loading from" 242 depends on FSL_LS_PPA 243 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 244 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 245 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 246 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A 247 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP 248 default 0x400000 if SYS_LS_PPA_FW_IN_MMC 249 default 0x400000 if SYS_LS_PPA_FW_IN_NAND 250 251 help 252 If the PPA firmware locate at XIP flash, such as NOR or 253 QSPI flash, this address is a directly memory-mapped. 254 If it is in a serial accessed flash, such as NAND and SD 255 card, it is a byte offset. 256 257config SYS_LS_PPA_ESBC_ADDR 258 hex "hdr address of PPA firmware loading from" 259 depends on FSL_LS_PPA && CHAIN_OF_TRUST 260 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 261 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 262 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 263 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 264 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 265 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A 266 default 0x680000 if SYS_LS_PPA_FW_IN_MMC 267 default 0x680000 if SYS_LS_PPA_FW_IN_NAND 268 help 269 If the PPA header firmware locate at XIP flash, such as NOR or 270 QSPI flash, this address is a directly memory-mapped. 271 If it is in a serial accessed flash, such as NAND and SD 272 card, it is a byte offset. 273 274config LS_PPA_ESBC_HDR_SIZE 275 hex "Length of PPA ESBC header" 276 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 277 default 0x2000 278 help 279 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 280 NAND to memory to validate PPA image. 281 282endmenu 283 284config SYS_FSL_ERRATUM_A008997 285 bool "Workaround for USB PHY erratum A008997" 286 287config SYS_FSL_ERRATUM_A009007 288 bool 289 help 290 Workaround for USB PHY erratum A009007 291 292config SYS_FSL_ERRATUM_A009008 293 bool "Workaround for USB PHY erratum A009008" 294 295config SYS_FSL_ERRATUM_A009798 296 bool "Workaround for USB PHY erratum A009798" 297 298config SYS_FSL_ERRATUM_A010315 299 bool "Workaround for PCIe erratum A010315" 300 301config SYS_FSL_ERRATUM_A010539 302 bool "Workaround for PIN MUX erratum A010539" 303 304config MAX_CPUS 305 int "Maximum number of CPUs permitted for Layerscape" 306 default 4 if ARCH_LS1043A 307 default 4 if ARCH_LS1046A 308 default 16 if ARCH_LS2080A 309 default 8 if ARCH_LS1088A 310 default 1 311 help 312 Set this number to the maximum number of possible CPUs in the SoC. 313 SoCs may have multiple clusters with each cluster may have multiple 314 ports. If some ports are reserved but higher ports are used for 315 cores, count the reserved ports. This will allocate enough memory 316 in spin table to properly handle all cores. 317 318config SECURE_BOOT 319 bool "Secure Boot" 320 help 321 Enable Freescale Secure Boot feature 322 323config QSPI_AHB_INIT 324 bool "Init the QSPI AHB bus" 325 help 326 The default setting for QSPI AHB bus just support 3bytes addressing. 327 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 328 bus for those flashes to support the full QSPI flash size. 329 330config SYS_CCI400_OFFSET 331 hex "Offset for CCI400 base" 332 depends on SYS_FSL_HAS_CCI400 333 default 0x3090000 if ARCH_LS1088A 334 default 0x180000 if FSL_LSCH2 335 help 336 Offset for CCI400 base 337 CCI400 base addr = CCSRBAR + CCI400_OFFSET 338 339config SYS_FSL_IFC_BANK_COUNT 340 int "Maximum banks of Integrated flash controller" 341 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A 342 default 4 if ARCH_LS1043A 343 default 4 if ARCH_LS1046A 344 default 8 if ARCH_LS2080A || ARCH_LS1088A 345 346config SYS_FSL_HAS_CCI400 347 bool 348 349config SYS_FSL_HAS_CCN504 350 bool 351 352config SYS_FSL_HAS_DP_DDR 353 bool 354 355config SYS_FSL_SRDS_1 356 bool 357 358config SYS_FSL_SRDS_2 359 bool 360 361config SYS_HAS_SERDES 362 bool 363 364config FSL_TZASC_1 365 bool 366 367config FSL_TZASC_2 368 bool 369 370endmenu 371 372menu "Layerscape clock tree configuration" 373 depends on FSL_LSCH2 || FSL_LSCH3 374 375config SYS_FSL_CLK 376 bool "Enable clock tree initialization" 377 default y 378 379config CLUSTER_CLK_FREQ 380 int "Reference clock of core cluster" 381 depends on ARCH_LS1012A 382 default 100000000 383 help 384 This number is the reference clock frequency of core PLL. 385 For most platforms, the core PLL and Platform PLL have the same 386 reference clock, but for some platforms, LS1012A for instance, 387 they are provided sepatately. 388 389config SYS_FSL_PCLK_DIV 390 int "Platform clock divider" 391 default 1 if ARCH_LS1043A 392 default 1 if ARCH_LS1046A 393 default 1 if ARCH_LS1088A 394 default 2 395 help 396 This is the divider that is used to derive Platform clock from 397 Platform PLL, in another word: 398 Platform_clk = Platform_PLL_freq / this_divider 399 400config SYS_FSL_DSPI_CLK_DIV 401 int "DSPI clock divider" 402 default 1 if ARCH_LS1043A 403 default 2 404 help 405 This is the divider that is used to derive DSPI clock from Platform 406 clock, in another word DSPI_clk = Platform_clk / this_divider. 407 408config SYS_FSL_DUART_CLK_DIV 409 int "DUART clock divider" 410 default 1 if ARCH_LS1043A 411 default 2 412 help 413 This is the divider that is used to derive DUART clock from Platform 414 clock, in another word DUART_clk = Platform_clk / this_divider. 415 416config SYS_FSL_I2C_CLK_DIV 417 int "I2C clock divider" 418 default 1 if ARCH_LS1043A 419 default 2 420 help 421 This is the divider that is used to derive I2C clock from Platform 422 clock, in another word I2C_clk = Platform_clk / this_divider. 423 424config SYS_FSL_IFC_CLK_DIV 425 int "IFC clock divider" 426 default 1 if ARCH_LS1043A 427 default 2 428 help 429 This is the divider that is used to derive IFC clock from Platform 430 clock, in another word IFC_clk = Platform_clk / this_divider. 431 432config SYS_FSL_LPUART_CLK_DIV 433 int "LPUART clock divider" 434 default 1 if ARCH_LS1043A 435 default 2 436 help 437 This is the divider that is used to derive LPUART clock from Platform 438 clock, in another word LPUART_clk = Platform_clk / this_divider. 439 440config SYS_FSL_SDHC_CLK_DIV 441 int "SDHC clock divider" 442 default 1 if ARCH_LS1043A 443 default 1 if ARCH_LS1012A 444 default 2 445 help 446 This is the divider that is used to derive SDHC clock from Platform 447 clock, in another word SDHC_clk = Platform_clk / this_divider. 448endmenu 449 450config RESV_RAM 451 bool 452 help 453 Reserve memory from the top, tracked by gd->arch.resv_ram. This 454 reserved RAM can be used by special driver that resides in memory 455 after U-Boot exits. It's up to implementation to allocate and allow 456 access to this reserved memory. For example, the reserved RAM can 457 be at the high end of physical memory. The reserve RAM may be 458 excluded from memory bank(s) passed to OS, or marked as reserved. 459 460config SYS_FSL_EC1 461 bool 462 help 463 Ethernet controller 1, this is connected to MAC3. 464 Provides DPAA2 capabilities 465 466config SYS_FSL_EC2 467 bool 468 help 469 Ethernet controller 2, this is connected to MAC4. 470 Provides DPAA2 capabilities 471 472config SYS_FSL_ERRATUM_A008336 473 bool 474 475config SYS_FSL_ERRATUM_A008514 476 bool 477 478config SYS_FSL_ERRATUM_A008585 479 bool 480 481config SYS_FSL_ERRATUM_A008850 482 bool 483 484config SYS_FSL_ERRATUM_A009203 485 bool 486 487config SYS_FSL_ERRATUM_A009635 488 bool 489 490config SYS_FSL_ERRATUM_A009660 491 bool 492 493config SYS_FSL_ERRATUM_A009929 494 bool 495 496 497config SYS_FSL_HAS_RGMII 498 bool 499 depends on SYS_FSL_EC1 || SYS_FSL_EC2 500 501 502config SYS_MC_RSV_MEM_ALIGN 503 hex "Management Complex reserved memory alignment" 504 depends on RESV_RAM 505 default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A 506 help 507 Reserved memory needs to be aligned for MC to use. Default value 508 is 512MB. 509 510config SPL_LDSCRIPT 511 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 512 513config HAS_FSL_XHCI_USB 514 bool 515 default y if ARCH_LS1043A || ARCH_LS1046A 516 help 517 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use 518 pins, select it when the pins are assigned to USB. 519