1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 select ARCH_EARLY_INIT_R 9 select BOARD_EARLY_INIT_F 10 11config ARCH_LS1043A 12 bool 13 select ARMV8_SET_SMPEN 14 select FSL_LSCH2 15 select SYS_FSL_DDR 16 select SYS_FSL_DDR_BE 17 select SYS_FSL_DDR_VER_50 18 select SYS_FSL_ERRATUM_A008850 19 select SYS_FSL_ERRATUM_A009660 20 select SYS_FSL_ERRATUM_A009663 21 select SYS_FSL_ERRATUM_A009929 22 select SYS_FSL_ERRATUM_A009942 23 select SYS_FSL_ERRATUM_A010315 24 select SYS_FSL_ERRATUM_A010539 25 select SYS_FSL_HAS_DDR3 26 select SYS_FSL_HAS_DDR4 27 select ARCH_EARLY_INIT_R 28 select BOARD_EARLY_INIT_F 29 imply SCSI 30 31config ARCH_LS1046A 32 bool 33 select ARMV8_SET_SMPEN 34 select FSL_LSCH2 35 select SYS_FSL_DDR 36 select SYS_FSL_DDR_BE 37 select SYS_FSL_DDR_VER_50 38 select SYS_FSL_ERRATUM_A008336 39 select SYS_FSL_ERRATUM_A008511 40 select SYS_FSL_ERRATUM_A008850 41 select SYS_FSL_ERRATUM_A009801 42 select SYS_FSL_ERRATUM_A009803 43 select SYS_FSL_ERRATUM_A009942 44 select SYS_FSL_ERRATUM_A010165 45 select SYS_FSL_ERRATUM_A010539 46 select SYS_FSL_HAS_DDR4 47 select SYS_FSL_SRDS_2 48 select ARCH_EARLY_INIT_R 49 select BOARD_EARLY_INIT_F 50 imply SCSI 51 52config ARCH_LS2080A 53 bool 54 select ARMV8_SET_SMPEN 55 select ARM_ERRATA_826974 56 select ARM_ERRATA_828024 57 select ARM_ERRATA_829520 58 select ARM_ERRATA_833471 59 select FSL_LSCH3 60 select SYS_FSL_DDR 61 select SYS_FSL_DDR_LE 62 select SYS_FSL_DDR_VER_50 63 select SYS_FSL_HAS_DP_DDR 64 select SYS_FSL_HAS_SEC 65 select SYS_FSL_HAS_DDR4 66 select SYS_FSL_SEC_COMPAT_5 67 select SYS_FSL_SEC_LE 68 select SYS_FSL_SRDS_2 69 select FSL_TZASC_1 70 select FSL_TZASC_2 71 select SYS_FSL_ERRATUM_A008336 72 select SYS_FSL_ERRATUM_A008511 73 select SYS_FSL_ERRATUM_A008514 74 select SYS_FSL_ERRATUM_A008585 75 select SYS_FSL_ERRATUM_A009635 76 select SYS_FSL_ERRATUM_A009663 77 select SYS_FSL_ERRATUM_A009801 78 select SYS_FSL_ERRATUM_A009803 79 select SYS_FSL_ERRATUM_A009942 80 select SYS_FSL_ERRATUM_A010165 81 select SYS_FSL_ERRATUM_A009203 82 select ARCH_EARLY_INIT_R 83 select BOARD_EARLY_INIT_F 84 85config FSL_LSCH2 86 bool 87 select SYS_FSL_HAS_SEC 88 select SYS_FSL_SEC_COMPAT_5 89 select SYS_FSL_SEC_BE 90 select SYS_FSL_SRDS_1 91 select SYS_HAS_SERDES 92 93config FSL_LSCH3 94 bool 95 select SYS_FSL_SRDS_1 96 select SYS_HAS_SERDES 97 98config FSL_MC_ENET 99 bool "Management Complex network" 100 depends on ARCH_LS2080A 101 default y 102 select RESV_RAM 103 help 104 Enable Management Complex (MC) network 105 106menu "Layerscape architecture" 107 depends on FSL_LSCH2 || FSL_LSCH3 108 109config FSL_PCIE_COMPAT 110 string "PCIe compatible of Kernel DT" 111 depends on PCIE_LAYERSCAPE 112 default "fsl,ls1012a-pcie" if ARCH_LS1012A 113 default "fsl,ls1043a-pcie" if ARCH_LS1043A 114 default "fsl,ls1046a-pcie" if ARCH_LS1046A 115 default "fsl,ls2080a-pcie" if ARCH_LS2080A 116 help 117 This compatible is used to find pci controller node in Kernel DT 118 to complete fixup. 119 120config HAS_FEATURE_GIC64K_ALIGN 121 bool 122 default y if ARCH_LS1043A 123 124config HAS_FEATURE_ENHANCED_MSI 125 bool 126 default y if ARCH_LS1043A 127 128menu "Layerscape PPA" 129config FSL_LS_PPA 130 bool "FSL Layerscape PPA firmware support" 131 depends on !ARMV8_PSCI 132 select ARMV8_SEC_FIRMWARE_SUPPORT 133 select SEC_FIRMWARE_ARMV8_PSCI 134 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 135 help 136 The FSL Primary Protected Application (PPA) is a software component 137 which is loaded during boot stage, and then remains resident in RAM 138 and runs in the TrustZone after boot. 139 Say y to enable it. 140 141config SPL_FSL_LS_PPA 142 bool "FSL Layerscape PPA firmware support for SPL build" 143 depends on !ARMV8_PSCI 144 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 145 select SEC_FIRMWARE_ARMV8_PSCI 146 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 147 help 148 The FSL Primary Protected Application (PPA) is a software component 149 which is loaded during boot stage, and then remains resident in RAM 150 and runs in the TrustZone after boot. This is to load PPA during SPL 151 stage instead of the RAM version of U-Boot. Once PPA is initialized, 152 the rest of U-Boot (including RAM version) runs at EL2. 153choice 154 prompt "FSL Layerscape PPA firmware loading-media select" 155 depends on FSL_LS_PPA 156 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 157 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 158 default SYS_LS_PPA_FW_IN_XIP 159 160config SYS_LS_PPA_FW_IN_XIP 161 bool "XIP" 162 help 163 Say Y here if the PPA firmware locate at XIP flash, such 164 as NOR or QSPI flash. 165 166config SYS_LS_PPA_FW_IN_MMC 167 bool "eMMC or SD Card" 168 help 169 Say Y here if the PPA firmware locate at eMMC/SD card. 170 171config SYS_LS_PPA_FW_IN_NAND 172 bool "NAND" 173 help 174 Say Y here if the PPA firmware locate at NAND flash. 175 176endchoice 177 178config SYS_LS_PPA_FW_ADDR 179 hex "Address of PPA firmware loading from" 180 depends on FSL_LS_PPA 181 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 182 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 183 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 184 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP 185 default 0x400000 if SYS_LS_PPA_FW_IN_MMC 186 default 0x400000 if SYS_LS_PPA_FW_IN_NAND 187 188 help 189 If the PPA firmware locate at XIP flash, such as NOR or 190 QSPI flash, this address is a directly memory-mapped. 191 If it is in a serial accessed flash, such as NAND and SD 192 card, it is a byte offset. 193 194config SYS_LS_PPA_ESBC_ADDR 195 hex "hdr address of PPA firmware loading from" 196 depends on FSL_LS_PPA && CHAIN_OF_TRUST 197 default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 198 default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 199 default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 200 default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3 201 default 0x700000 if SYS_LS_PPA_FW_IN_MMC 202 default 0x700000 if SYS_LS_PPA_FW_IN_NAND 203 help 204 If the PPA header firmware locate at XIP flash, such as NOR or 205 QSPI flash, this address is a directly memory-mapped. 206 If it is in a serial accessed flash, such as NAND and SD 207 card, it is a byte offset. 208 209config LS_PPA_ESBC_HDR_SIZE 210 hex "Length of PPA ESBC header" 211 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 212 default 0x2000 213 help 214 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 215 NAND to memory to validate PPA image. 216 217endmenu 218 219config SYS_FSL_ERRATUM_A010315 220 bool "Workaround for PCIe erratum A010315" 221 222config SYS_FSL_ERRATUM_A010539 223 bool "Workaround for PIN MUX erratum A010539" 224 225config MAX_CPUS 226 int "Maximum number of CPUs permitted for Layerscape" 227 default 4 if ARCH_LS1043A 228 default 4 if ARCH_LS1046A 229 default 16 if ARCH_LS2080A 230 default 1 231 help 232 Set this number to the maximum number of possible CPUs in the SoC. 233 SoCs may have multiple clusters with each cluster may have multiple 234 ports. If some ports are reserved but higher ports are used for 235 cores, count the reserved ports. This will allocate enough memory 236 in spin table to properly handle all cores. 237 238config SECURE_BOOT 239 bool "Secure Boot" 240 help 241 Enable Freescale Secure Boot feature 242 243config QSPI_AHB_INIT 244 bool "Init the QSPI AHB bus" 245 help 246 The default setting for QSPI AHB bus just support 3bytes addressing. 247 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 248 bus for those flashes to support the full QSPI flash size. 249 250config SYS_FSL_IFC_BANK_COUNT 251 int "Maximum banks of Integrated flash controller" 252 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 253 default 4 if ARCH_LS1043A 254 default 4 if ARCH_LS1046A 255 default 8 if ARCH_LS2080A 256 257config SYS_FSL_HAS_DP_DDR 258 bool 259 260config SYS_FSL_SRDS_1 261 bool 262 263config SYS_FSL_SRDS_2 264 bool 265 266config SYS_HAS_SERDES 267 bool 268 269config FSL_TZASC_1 270 bool 271 272config FSL_TZASC_2 273 bool 274 275endmenu 276 277menu "Layerscape clock tree configuration" 278 depends on FSL_LSCH2 || FSL_LSCH3 279 280config SYS_FSL_CLK 281 bool "Enable clock tree initialization" 282 default y 283 284config CLUSTER_CLK_FREQ 285 int "Reference clock of core cluster" 286 depends on ARCH_LS1012A 287 default 100000000 288 help 289 This number is the reference clock frequency of core PLL. 290 For most platforms, the core PLL and Platform PLL have the same 291 reference clock, but for some platforms, LS1012A for instance, 292 they are provided sepatately. 293 294config SYS_FSL_PCLK_DIV 295 int "Platform clock divider" 296 default 1 if ARCH_LS1043A 297 default 1 if ARCH_LS1046A 298 default 2 299 help 300 This is the divider that is used to derive Platform clock from 301 Platform PLL, in another word: 302 Platform_clk = Platform_PLL_freq / this_divider 303 304config SYS_FSL_DSPI_CLK_DIV 305 int "DSPI clock divider" 306 default 1 if ARCH_LS1043A 307 default 2 308 help 309 This is the divider that is used to derive DSPI clock from Platform 310 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. 311 312config SYS_FSL_DUART_CLK_DIV 313 int "DUART clock divider" 314 default 1 if ARCH_LS1043A 315 default 2 316 help 317 This is the divider that is used to derive DUART clock from Platform 318 clock, in another word DUART_clk = Platform_clk / this_divider. 319 320config SYS_FSL_I2C_CLK_DIV 321 int "I2C clock divider" 322 default 1 if ARCH_LS1043A 323 default 2 324 help 325 This is the divider that is used to derive I2C clock from Platform 326 clock, in another word I2C_clk = Platform_clk / this_divider. 327 328config SYS_FSL_IFC_CLK_DIV 329 int "IFC clock divider" 330 default 1 if ARCH_LS1043A 331 default 2 332 help 333 This is the divider that is used to derive IFC clock from Platform 334 clock, in another word IFC_clk = Platform_clk / this_divider. 335 336config SYS_FSL_LPUART_CLK_DIV 337 int "LPUART clock divider" 338 default 1 if ARCH_LS1043A 339 default 2 340 help 341 This is the divider that is used to derive LPUART clock from Platform 342 clock, in another word LPUART_clk = Platform_clk / this_divider. 343 344config SYS_FSL_SDHC_CLK_DIV 345 int "SDHC clock divider" 346 default 1 if ARCH_LS1043A 347 default 1 if ARCH_LS1012A 348 default 2 349 help 350 This is the divider that is used to derive SDHC clock from Platform 351 clock, in another word SDHC_clk = Platform_clk / this_divider. 352endmenu 353 354config RESV_RAM 355 bool 356 help 357 Reserve memory from the top, tracked by gd->arch.resv_ram. This 358 reserved RAM can be used by special driver that resides in memory 359 after U-Boot exits. It's up to implementation to allocate and allow 360 access to this reserved memory. For example, the reserved RAM can 361 be at the high end of physical memory. The reserve RAM may be 362 excluded from memory bank(s) passed to OS, or marked as reserved. 363 364config SYS_FSL_ERRATUM_A008336 365 bool 366 367config SYS_FSL_ERRATUM_A008514 368 bool 369 370config SYS_FSL_ERRATUM_A008585 371 bool 372 373config SYS_FSL_ERRATUM_A008850 374 bool 375 376config SYS_FSL_ERRATUM_A009203 377 bool 378 379config SYS_FSL_ERRATUM_A009635 380 bool 381 382config SYS_FSL_ERRATUM_A009660 383 bool 384 385config SYS_FSL_ERRATUM_A009929 386 bool 387 388config SYS_MC_RSV_MEM_ALIGN 389 hex "Management Complex reserved memory alignment" 390 depends on RESV_RAM 391 default 0x20000000 392 help 393 Reserved memory needs to be aligned for MC to use. Default value 394 is 512MB. 395