1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 select ARCH_EARLY_INIT_R 9 select BOARD_EARLY_INIT_F 10 11config ARCH_LS1043A 12 bool 13 select ARMV8_SET_SMPEN 14 select FSL_LSCH2 15 select SYS_FSL_DDR 16 select SYS_FSL_DDR_BE 17 select SYS_FSL_DDR_VER_50 18 select SYS_FSL_ERRATUM_A008850 19 select SYS_FSL_ERRATUM_A009660 20 select SYS_FSL_ERRATUM_A009663 21 select SYS_FSL_ERRATUM_A009929 22 select SYS_FSL_ERRATUM_A009942 23 select SYS_FSL_ERRATUM_A010315 24 select SYS_FSL_ERRATUM_A010539 25 select SYS_FSL_HAS_DDR3 26 select SYS_FSL_HAS_DDR4 27 select ARCH_EARLY_INIT_R 28 select BOARD_EARLY_INIT_F 29 30config ARCH_LS1046A 31 bool 32 select ARMV8_SET_SMPEN 33 select FSL_LSCH2 34 select SYS_FSL_DDR 35 select SYS_FSL_DDR_BE 36 select SYS_FSL_DDR_VER_50 37 select SYS_FSL_ERRATUM_A008336 38 select SYS_FSL_ERRATUM_A008511 39 select SYS_FSL_ERRATUM_A008850 40 select SYS_FSL_ERRATUM_A009801 41 select SYS_FSL_ERRATUM_A009803 42 select SYS_FSL_ERRATUM_A009942 43 select SYS_FSL_ERRATUM_A010165 44 select SYS_FSL_ERRATUM_A010539 45 select SYS_FSL_HAS_DDR4 46 select SYS_FSL_SRDS_2 47 select ARCH_EARLY_INIT_R 48 select BOARD_EARLY_INIT_F 49 50config ARCH_LS2080A 51 bool 52 select ARMV8_SET_SMPEN 53 select ARM_ERRATA_826974 54 select ARM_ERRATA_828024 55 select ARM_ERRATA_829520 56 select ARM_ERRATA_833471 57 select FSL_LSCH3 58 select SYS_FSL_DDR 59 select SYS_FSL_DDR_LE 60 select SYS_FSL_DDR_VER_50 61 select SYS_FSL_HAS_DP_DDR 62 select SYS_FSL_HAS_SEC 63 select SYS_FSL_HAS_DDR4 64 select SYS_FSL_SEC_COMPAT_5 65 select SYS_FSL_SEC_LE 66 select SYS_FSL_SRDS_2 67 select FSL_TZASC_1 68 select FSL_TZASC_2 69 select SYS_FSL_ERRATUM_A008336 70 select SYS_FSL_ERRATUM_A008511 71 select SYS_FSL_ERRATUM_A008514 72 select SYS_FSL_ERRATUM_A008585 73 select SYS_FSL_ERRATUM_A009635 74 select SYS_FSL_ERRATUM_A009663 75 select SYS_FSL_ERRATUM_A009801 76 select SYS_FSL_ERRATUM_A009803 77 select SYS_FSL_ERRATUM_A009942 78 select SYS_FSL_ERRATUM_A010165 79 select SYS_FSL_ERRATUM_A009203 80 select ARCH_EARLY_INIT_R 81 select BOARD_EARLY_INIT_F 82 83config FSL_LSCH2 84 bool 85 select SYS_FSL_HAS_SEC 86 select SYS_FSL_SEC_COMPAT_5 87 select SYS_FSL_SEC_BE 88 select SYS_FSL_SRDS_1 89 select SYS_HAS_SERDES 90 91config FSL_LSCH3 92 bool 93 select SYS_FSL_SRDS_1 94 select SYS_HAS_SERDES 95 96config FSL_MC_ENET 97 bool "Management Complex network" 98 depends on ARCH_LS2080A 99 default y 100 select RESV_RAM 101 help 102 Enable Management Complex (MC) network 103 104menu "Layerscape architecture" 105 depends on FSL_LSCH2 || FSL_LSCH3 106 107config FSL_PCIE_COMPAT 108 string "PCIe compatible of Kernel DT" 109 depends on PCIE_LAYERSCAPE 110 default "fsl,ls1012a-pcie" if ARCH_LS1012A 111 default "fsl,ls1043a-pcie" if ARCH_LS1043A 112 default "fsl,ls1046a-pcie" if ARCH_LS1046A 113 default "fsl,ls2080a-pcie" if ARCH_LS2080A 114 help 115 This compatible is used to find pci controller node in Kernel DT 116 to complete fixup. 117 118config HAS_FEATURE_GIC64K_ALIGN 119 bool 120 default y if ARCH_LS1043A 121 122config HAS_FEATURE_ENHANCED_MSI 123 bool 124 default y if ARCH_LS1043A 125 126menu "Layerscape PPA" 127config FSL_LS_PPA 128 bool "FSL Layerscape PPA firmware support" 129 depends on !ARMV8_PSCI 130 select ARMV8_SEC_FIRMWARE_SUPPORT 131 select SEC_FIRMWARE_ARMV8_PSCI 132 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 133 help 134 The FSL Primary Protected Application (PPA) is a software component 135 which is loaded during boot stage, and then remains resident in RAM 136 and runs in the TrustZone after boot. 137 Say y to enable it. 138choice 139 prompt "FSL Layerscape PPA firmware loading-media select" 140 depends on FSL_LS_PPA 141 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 142 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 143 default SYS_LS_PPA_FW_IN_XIP 144 145config SYS_LS_PPA_FW_IN_XIP 146 bool "XIP" 147 help 148 Say Y here if the PPA firmware locate at XIP flash, such 149 as NOR or QSPI flash. 150 151config SYS_LS_PPA_FW_IN_MMC 152 bool "eMMC or SD Card" 153 help 154 Say Y here if the PPA firmware locate at eMMC/SD card. 155 156config SYS_LS_PPA_FW_IN_NAND 157 bool "NAND" 158 help 159 Say Y here if the PPA firmware locate at NAND flash. 160 161endchoice 162 163config SYS_LS_PPA_FW_ADDR 164 hex "Address of PPA firmware loading from" 165 depends on FSL_LS_PPA 166 default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 167 default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 168 default 0x60500000 if SYS_LS_PPA_FW_IN_XIP 169 default 0x500000 if SYS_LS_PPA_FW_IN_MMC 170 default 0x500000 if SYS_LS_PPA_FW_IN_NAND 171 172 help 173 If the PPA firmware locate at XIP flash, such as NOR or 174 QSPI flash, this address is a directly memory-mapped. 175 If it is in a serial accessed flash, such as NAND and SD 176 card, it is a byte offset. 177 178config SYS_LS_PPA_ESBC_ADDR 179 hex "hdr address of PPA firmware loading from" 180 depends on FSL_LS_PPA && CHAIN_OF_TRUST 181 default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 182 default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 183 default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 184 default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3 185 help 186 If the PPA header firmware locate at XIP flash, such as NOR or 187 QSPI flash, this address is a directly memory-mapped. 188 If it is in a serial accessed flash, such as NAND and SD 189 card, it is a byte offset. 190 191endmenu 192 193config SYS_FSL_ERRATUM_A010315 194 bool "Workaround for PCIe erratum A010315" 195 196config SYS_FSL_ERRATUM_A010539 197 bool "Workaround for PIN MUX erratum A010539" 198 199config MAX_CPUS 200 int "Maximum number of CPUs permitted for Layerscape" 201 default 4 if ARCH_LS1043A 202 default 4 if ARCH_LS1046A 203 default 16 if ARCH_LS2080A 204 default 1 205 help 206 Set this number to the maximum number of possible CPUs in the SoC. 207 SoCs may have multiple clusters with each cluster may have multiple 208 ports. If some ports are reserved but higher ports are used for 209 cores, count the reserved ports. This will allocate enough memory 210 in spin table to properly handle all cores. 211 212config SECURE_BOOT 213 bool "Secure Boot" 214 help 215 Enable Freescale Secure Boot feature 216 217config QSPI_AHB_INIT 218 bool "Init the QSPI AHB bus" 219 help 220 The default setting for QSPI AHB bus just support 3bytes addressing. 221 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 222 bus for those flashes to support the full QSPI flash size. 223 224config SYS_FSL_IFC_BANK_COUNT 225 int "Maximum banks of Integrated flash controller" 226 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 227 default 4 if ARCH_LS1043A 228 default 4 if ARCH_LS1046A 229 default 8 if ARCH_LS2080A 230 231config SYS_FSL_HAS_DP_DDR 232 bool 233 234config SYS_FSL_SRDS_1 235 bool 236 237config SYS_FSL_SRDS_2 238 bool 239 240config SYS_HAS_SERDES 241 bool 242 243config FSL_TZASC_1 244 bool 245 246config FSL_TZASC_2 247 bool 248 249endmenu 250 251menu "Layerscape clock tree configuration" 252 depends on FSL_LSCH2 || FSL_LSCH3 253 254config SYS_FSL_CLK 255 bool "Enable clock tree initialization" 256 default y 257 258config CLUSTER_CLK_FREQ 259 int "Reference clock of core cluster" 260 depends on ARCH_LS1012A 261 default 100000000 262 help 263 This number is the reference clock frequency of core PLL. 264 For most platforms, the core PLL and Platform PLL have the same 265 reference clock, but for some platforms, LS1012A for instance, 266 they are provided sepatately. 267 268config SYS_FSL_PCLK_DIV 269 int "Platform clock divider" 270 default 1 if ARCH_LS1043A 271 default 1 if ARCH_LS1046A 272 default 2 273 help 274 This is the divider that is used to derive Platform clock from 275 Platform PLL, in another word: 276 Platform_clk = Platform_PLL_freq / this_divider 277 278config SYS_FSL_DSPI_CLK_DIV 279 int "DSPI clock divider" 280 default 1 if ARCH_LS1043A 281 default 2 282 help 283 This is the divider that is used to derive DSPI clock from Platform 284 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. 285 286config SYS_FSL_DUART_CLK_DIV 287 int "DUART clock divider" 288 default 1 if ARCH_LS1043A 289 default 2 290 help 291 This is the divider that is used to derive DUART clock from Platform 292 clock, in another word DUART_clk = Platform_clk / this_divider. 293 294config SYS_FSL_I2C_CLK_DIV 295 int "I2C clock divider" 296 default 1 if ARCH_LS1043A 297 default 2 298 help 299 This is the divider that is used to derive I2C clock from Platform 300 clock, in another word I2C_clk = Platform_clk / this_divider. 301 302config SYS_FSL_IFC_CLK_DIV 303 int "IFC clock divider" 304 default 1 if ARCH_LS1043A 305 default 2 306 help 307 This is the divider that is used to derive IFC clock from Platform 308 clock, in another word IFC_clk = Platform_clk / this_divider. 309 310config SYS_FSL_LPUART_CLK_DIV 311 int "LPUART clock divider" 312 default 1 if ARCH_LS1043A 313 default 2 314 help 315 This is the divider that is used to derive LPUART clock from Platform 316 clock, in another word LPUART_clk = Platform_clk / this_divider. 317 318config SYS_FSL_SDHC_CLK_DIV 319 int "SDHC clock divider" 320 default 1 if ARCH_LS1043A 321 default 1 if ARCH_LS1012A 322 default 2 323 help 324 This is the divider that is used to derive SDHC clock from Platform 325 clock, in another word SDHC_clk = Platform_clk / this_divider. 326endmenu 327 328config RESV_RAM 329 bool 330 help 331 Reserve memory from the top, tracked by gd->arch.resv_ram. This 332 reserved RAM can be used by special driver that resides in memory 333 after U-Boot exits. It's up to implementation to allocate and allow 334 access to this reserved memory. For example, the reserved RAM can 335 be at the high end of physical memory. The reserve RAM may be 336 excluded from memory bank(s) passed to OS, or marked as reserved. 337 338config SYS_FSL_ERRATUM_A008336 339 bool 340 341config SYS_FSL_ERRATUM_A008514 342 bool 343 344config SYS_FSL_ERRATUM_A008585 345 bool 346 347config SYS_FSL_ERRATUM_A008850 348 bool 349 350config SYS_FSL_ERRATUM_A009203 351 bool 352 353config SYS_FSL_ERRATUM_A009635 354 bool 355 356config SYS_FSL_ERRATUM_A009660 357 bool 358 359config SYS_FSL_ERRATUM_A009929 360 bool 361 362config SYS_MC_RSV_MEM_ALIGN 363 hex "Management Complex reserved memory alignment" 364 depends on RESV_RAM 365 default 0x20000000 366 help 367 Reserved memory needs to be aligned for MC to use. Default value 368 is 512MB. 369