1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 select ARCH_EARLY_INIT_R 9 select BOARD_EARLY_INIT_F 10 11config ARCH_LS1043A 12 bool 13 select ARMV8_SET_SMPEN 14 select FSL_LSCH2 15 select SYS_FSL_DDR 16 select SYS_FSL_DDR_BE 17 select SYS_FSL_DDR_VER_50 18 select SYS_FSL_ERRATUM_A008850 19 select SYS_FSL_ERRATUM_A009660 20 select SYS_FSL_ERRATUM_A009663 21 select SYS_FSL_ERRATUM_A009929 22 select SYS_FSL_ERRATUM_A009942 23 select SYS_FSL_ERRATUM_A010315 24 select SYS_FSL_ERRATUM_A010539 25 select SYS_FSL_HAS_DDR3 26 select SYS_FSL_HAS_DDR4 27 select ARCH_EARLY_INIT_R 28 select BOARD_EARLY_INIT_F 29 30config ARCH_LS1046A 31 bool 32 select ARMV8_SET_SMPEN 33 select FSL_LSCH2 34 select SYS_FSL_DDR 35 select SYS_FSL_DDR_BE 36 select SYS_FSL_DDR_VER_50 37 select SYS_FSL_ERRATUM_A008336 38 select SYS_FSL_ERRATUM_A008511 39 select SYS_FSL_ERRATUM_A008850 40 select SYS_FSL_ERRATUM_A009801 41 select SYS_FSL_ERRATUM_A009803 42 select SYS_FSL_ERRATUM_A009942 43 select SYS_FSL_ERRATUM_A010165 44 select SYS_FSL_ERRATUM_A010539 45 select SYS_FSL_HAS_DDR4 46 select SYS_FSL_SRDS_2 47 select ARCH_EARLY_INIT_R 48 select BOARD_EARLY_INIT_F 49 50config ARCH_LS2080A 51 bool 52 select ARMV8_SET_SMPEN 53 select ARM_ERRATA_826974 54 select ARM_ERRATA_828024 55 select ARM_ERRATA_829520 56 select ARM_ERRATA_833471 57 select FSL_LSCH3 58 select SYS_FSL_DDR 59 select SYS_FSL_DDR_LE 60 select SYS_FSL_DDR_VER_50 61 select SYS_FSL_HAS_DP_DDR 62 select SYS_FSL_HAS_SEC 63 select SYS_FSL_HAS_DDR4 64 select SYS_FSL_SEC_COMPAT_5 65 select SYS_FSL_SEC_LE 66 select SYS_FSL_SRDS_2 67 select FSL_TZASC_1 68 select FSL_TZASC_2 69 select SYS_FSL_ERRATUM_A008336 70 select SYS_FSL_ERRATUM_A008511 71 select SYS_FSL_ERRATUM_A008514 72 select SYS_FSL_ERRATUM_A008585 73 select SYS_FSL_ERRATUM_A009635 74 select SYS_FSL_ERRATUM_A009663 75 select SYS_FSL_ERRATUM_A009801 76 select SYS_FSL_ERRATUM_A009803 77 select SYS_FSL_ERRATUM_A009942 78 select SYS_FSL_ERRATUM_A010165 79 select SYS_FSL_ERRATUM_A009203 80 select ARCH_EARLY_INIT_R 81 select BOARD_EARLY_INIT_F 82 83config FSL_LSCH2 84 bool 85 select SYS_FSL_HAS_SEC 86 select SYS_FSL_SEC_COMPAT_5 87 select SYS_FSL_SEC_BE 88 select SYS_FSL_SRDS_1 89 select SYS_HAS_SERDES 90 91config FSL_LSCH3 92 bool 93 select SYS_FSL_SRDS_1 94 select SYS_HAS_SERDES 95 96config FSL_MC_ENET 97 bool "Management Complex network" 98 depends on ARCH_LS2080A 99 default y 100 select RESV_RAM 101 help 102 Enable Management Complex (MC) network 103 104menu "Layerscape architecture" 105 depends on FSL_LSCH2 || FSL_LSCH3 106 107config FSL_PCIE_COMPAT 108 string "PCIe compatible of Kernel DT" 109 depends on PCIE_LAYERSCAPE 110 default "fsl,ls1012a-pcie" if ARCH_LS1012A 111 default "fsl,ls1043a-pcie" if ARCH_LS1043A 112 default "fsl,ls1046a-pcie" if ARCH_LS1046A 113 default "fsl,ls2080a-pcie" if ARCH_LS2080A 114 help 115 This compatible is used to find pci controller node in Kernel DT 116 to complete fixup. 117 118config HAS_FEATURE_GIC64K_ALIGN 119 bool 120 default y if ARCH_LS1043A 121 122config HAS_FEATURE_ENHANCED_MSI 123 bool 124 default y if ARCH_LS1043A 125 126menu "Layerscape PPA" 127config FSL_LS_PPA 128 bool "FSL Layerscape PPA firmware support" 129 depends on !ARMV8_PSCI 130 select ARMV8_SEC_FIRMWARE_SUPPORT 131 select SEC_FIRMWARE_ARMV8_PSCI 132 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 133 help 134 The FSL Primary Protected Application (PPA) is a software component 135 which is loaded during boot stage, and then remains resident in RAM 136 and runs in the TrustZone after boot. 137 Say y to enable it. 138choice 139 prompt "FSL Layerscape PPA firmware loading-media select" 140 depends on FSL_LS_PPA 141 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 142 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 143 default SYS_LS_PPA_FW_IN_XIP 144 145config SYS_LS_PPA_FW_IN_XIP 146 bool "XIP" 147 help 148 Say Y here if the PPA firmware locate at XIP flash, such 149 as NOR or QSPI flash. 150 151config SYS_LS_PPA_FW_IN_MMC 152 bool "eMMC or SD Card" 153 help 154 Say Y here if the PPA firmware locate at eMMC/SD card. 155 156config SYS_LS_PPA_FW_IN_NAND 157 bool "NAND" 158 help 159 Say Y here if the PPA firmware locate at NAND flash. 160 161endchoice 162 163config SYS_LS_PPA_FW_ADDR 164 hex "Address of PPA firmware loading from" 165 depends on FSL_LS_PPA 166 default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 167 default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 168 default 0x60500000 if SYS_LS_PPA_FW_IN_XIP 169 default 0x500000 if SYS_LS_PPA_FW_IN_MMC 170 default 0x500000 if SYS_LS_PPA_FW_IN_NAND 171 172 help 173 If the PPA firmware locate at XIP flash, such as NOR or 174 QSPI flash, this address is a directly memory-mapped. 175 If it is in a serial accessed flash, such as NAND and SD 176 card, it is a byte offset. 177 178config SYS_LS_PPA_ESBC_ADDR 179 hex "hdr address of PPA firmware loading from" 180 depends on FSL_LS_PPA && CHAIN_OF_TRUST 181 default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 182 default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 183 default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 184 default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3 185 default 0x700000 if SYS_LS_PPA_FW_IN_MMC 186 default 0x700000 if SYS_LS_PPA_FW_IN_NAND 187 help 188 If the PPA header firmware locate at XIP flash, such as NOR or 189 QSPI flash, this address is a directly memory-mapped. 190 If it is in a serial accessed flash, such as NAND and SD 191 card, it is a byte offset. 192 193config LS_PPA_ESBC_HDR_SIZE 194 hex "Length of PPA ESBC header" 195 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 196 default 0x2000 197 help 198 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 199 NAND to memory to validate PPA image. 200 201endmenu 202 203config SYS_FSL_ERRATUM_A010315 204 bool "Workaround for PCIe erratum A010315" 205 206config SYS_FSL_ERRATUM_A010539 207 bool "Workaround for PIN MUX erratum A010539" 208 209config MAX_CPUS 210 int "Maximum number of CPUs permitted for Layerscape" 211 default 4 if ARCH_LS1043A 212 default 4 if ARCH_LS1046A 213 default 16 if ARCH_LS2080A 214 default 1 215 help 216 Set this number to the maximum number of possible CPUs in the SoC. 217 SoCs may have multiple clusters with each cluster may have multiple 218 ports. If some ports are reserved but higher ports are used for 219 cores, count the reserved ports. This will allocate enough memory 220 in spin table to properly handle all cores. 221 222config SECURE_BOOT 223 bool "Secure Boot" 224 help 225 Enable Freescale Secure Boot feature 226 227config QSPI_AHB_INIT 228 bool "Init the QSPI AHB bus" 229 help 230 The default setting for QSPI AHB bus just support 3bytes addressing. 231 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 232 bus for those flashes to support the full QSPI flash size. 233 234config SYS_FSL_IFC_BANK_COUNT 235 int "Maximum banks of Integrated flash controller" 236 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 237 default 4 if ARCH_LS1043A 238 default 4 if ARCH_LS1046A 239 default 8 if ARCH_LS2080A 240 241config SYS_FSL_HAS_DP_DDR 242 bool 243 244config SYS_FSL_SRDS_1 245 bool 246 247config SYS_FSL_SRDS_2 248 bool 249 250config SYS_HAS_SERDES 251 bool 252 253config FSL_TZASC_1 254 bool 255 256config FSL_TZASC_2 257 bool 258 259endmenu 260 261menu "Layerscape clock tree configuration" 262 depends on FSL_LSCH2 || FSL_LSCH3 263 264config SYS_FSL_CLK 265 bool "Enable clock tree initialization" 266 default y 267 268config CLUSTER_CLK_FREQ 269 int "Reference clock of core cluster" 270 depends on ARCH_LS1012A 271 default 100000000 272 help 273 This number is the reference clock frequency of core PLL. 274 For most platforms, the core PLL and Platform PLL have the same 275 reference clock, but for some platforms, LS1012A for instance, 276 they are provided sepatately. 277 278config SYS_FSL_PCLK_DIV 279 int "Platform clock divider" 280 default 1 if ARCH_LS1043A 281 default 1 if ARCH_LS1046A 282 default 2 283 help 284 This is the divider that is used to derive Platform clock from 285 Platform PLL, in another word: 286 Platform_clk = Platform_PLL_freq / this_divider 287 288config SYS_FSL_DSPI_CLK_DIV 289 int "DSPI clock divider" 290 default 1 if ARCH_LS1043A 291 default 2 292 help 293 This is the divider that is used to derive DSPI clock from Platform 294 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. 295 296config SYS_FSL_DUART_CLK_DIV 297 int "DUART clock divider" 298 default 1 if ARCH_LS1043A 299 default 2 300 help 301 This is the divider that is used to derive DUART clock from Platform 302 clock, in another word DUART_clk = Platform_clk / this_divider. 303 304config SYS_FSL_I2C_CLK_DIV 305 int "I2C clock divider" 306 default 1 if ARCH_LS1043A 307 default 2 308 help 309 This is the divider that is used to derive I2C clock from Platform 310 clock, in another word I2C_clk = Platform_clk / this_divider. 311 312config SYS_FSL_IFC_CLK_DIV 313 int "IFC clock divider" 314 default 1 if ARCH_LS1043A 315 default 2 316 help 317 This is the divider that is used to derive IFC clock from Platform 318 clock, in another word IFC_clk = Platform_clk / this_divider. 319 320config SYS_FSL_LPUART_CLK_DIV 321 int "LPUART clock divider" 322 default 1 if ARCH_LS1043A 323 default 2 324 help 325 This is the divider that is used to derive LPUART clock from Platform 326 clock, in another word LPUART_clk = Platform_clk / this_divider. 327 328config SYS_FSL_SDHC_CLK_DIV 329 int "SDHC clock divider" 330 default 1 if ARCH_LS1043A 331 default 1 if ARCH_LS1012A 332 default 2 333 help 334 This is the divider that is used to derive SDHC clock from Platform 335 clock, in another word SDHC_clk = Platform_clk / this_divider. 336endmenu 337 338config RESV_RAM 339 bool 340 help 341 Reserve memory from the top, tracked by gd->arch.resv_ram. This 342 reserved RAM can be used by special driver that resides in memory 343 after U-Boot exits. It's up to implementation to allocate and allow 344 access to this reserved memory. For example, the reserved RAM can 345 be at the high end of physical memory. The reserve RAM may be 346 excluded from memory bank(s) passed to OS, or marked as reserved. 347 348config SYS_FSL_ERRATUM_A008336 349 bool 350 351config SYS_FSL_ERRATUM_A008514 352 bool 353 354config SYS_FSL_ERRATUM_A008585 355 bool 356 357config SYS_FSL_ERRATUM_A008850 358 bool 359 360config SYS_FSL_ERRATUM_A009203 361 bool 362 363config SYS_FSL_ERRATUM_A009635 364 bool 365 366config SYS_FSL_ERRATUM_A009660 367 bool 368 369config SYS_FSL_ERRATUM_A009929 370 bool 371 372config SYS_MC_RSV_MEM_ALIGN 373 hex "Management Complex reserved memory alignment" 374 depends on RESV_RAM 375 default 0x20000000 376 help 377 Reserved memory needs to be aligned for MC to use. Default value 378 is 512MB. 379