1config ARCH_LS1012A
2	bool
3	select FSL_LSCH2
4	select SYS_FSL_DDR_BE
5	select SYS_FSL_MMDC
6	select SYS_FSL_ERRATUM_A010315
7
8config ARCH_LS1043A
9	bool
10	select FSL_LSCH2
11	select SYS_FSL_DDR_BE
12	select SYS_FSL_DDR_VER_50
13	select SYS_FSL_ERRATUM_A010315
14	select SYS_FSL_ERRATUM_A010539
15
16config ARCH_LS1046A
17	bool
18	select FSL_LSCH2
19	select SYS_FSL_DDR_BE
20	select SYS_FSL_DDR4
21	select SYS_FSL_DDR_VER_50
22	select SYS_FSL_ERRATUM_A010539
23	select SYS_FSL_SRDS_2
24
25config ARCH_LS2080A
26	bool
27	select FSL_LSCH3
28	select SYS_FSL_DDR4
29	select SYS_FSL_DDR_LE
30	select SYS_FSL_DDR_VER_50
31	select SYS_FSL_HAS_DP_DDR
32	select SYS_FSL_SRDS_2
33
34config FSL_LSCH2
35	bool
36	select SYS_FSL_SRDS_1
37	select SYS_HAS_SERDES
38
39config FSL_LSCH3
40	bool
41	select SYS_FSL_SRDS_1
42	select SYS_HAS_SERDES
43
44menu "Layerscape architecture"
45	depends on FSL_LSCH2 || FSL_LSCH3
46
47config SYS_FSL_MMDC
48	bool
49
50config SYS_FSL_ERRATUM_A010315
51	bool "Workaround for PCIe erratum A010315"
52
53config SYS_FSL_ERRATUM_A010539
54	bool "Workaround for PIN MUX erratum A010539"
55
56config MAX_CPUS
57	int "Maximum number of CPUs permitted for Layerscape"
58	default 4 if ARCH_LS1043A
59	default 4 if ARCH_LS1046A
60	default 16 if ARCH_LS2080A
61	default 1
62	help
63	  Set this number to the maximum number of possible CPUs in the SoC.
64	  SoCs may have multiple clusters with each cluster may have multiple
65	  ports. If some ports are reserved but higher ports are used for
66	  cores, count the reserved ports. This will allocate enough memory
67	  in spin table to properly handle all cores.
68
69config NUM_DDR_CONTROLLERS
70	int "Maximum DDR controllers"
71	default 3 if ARCH_LS2080A
72	default 1
73
74config SYS_FSL_IFC_BANK_COUNT
75	int "Maximum banks of Integrated flash controller"
76	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
77	default 4 if ARCH_LS1043A
78	default 4 if ARCH_LS1046A
79	default 8 if ARCH_LS2080A
80
81config SYS_FSL_HAS_DP_DDR
82	bool
83
84config SYS_FSL_SRDS_1
85	bool
86
87config SYS_FSL_SRDS_2
88	bool
89
90config SYS_HAS_SERDES
91	bool
92
93config SYS_FSL_DDR
94	bool "Freescale DDR driver"
95	help
96	  Select Freescale General DDR driver, shared between most Freescale
97	  PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
98	  based Layerscape SoCs (such as ls2080a).
99
100config SYS_FSL_DDR_BE
101	bool
102	help
103	  Access DDR registers in big-endian.
104
105config SYS_FSL_DDR_LE
106	bool
107	help
108	  Access DDR registers in little-endian.
109
110config SYS_FSL_DDR_VER
111	int
112	default 50 if SYS_FSL_DDR_VER_50
113
114config SYS_FSL_DDR_VER_50
115	bool
116
117config SYS_FSL_DDRC_ARM_GEN3
118	bool
119
120config SYS_FSL_DDRC_GEN4
121	bool
122
123config SYS_FSL_DDR3
124	bool "Freescale DDR3 controller"
125	depends on !SYS_FSL_DDR4
126	select SYS_FSL_DDR
127	select SYS_FSL_DDRC_ARM_GEN3
128	help
129	  Enable Freescale DDR3 controller on ARM-based SoCs.
130
131config SYS_FSL_DDR4
132	bool "Freescale DDR4 controller"
133	select SYS_FSL_DDR
134	select SYS_FSL_DDRC_GEN4
135	help
136	  Enable Freescale DDR4 controller.
137
138endmenu
139