1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 select ARCH_EARLY_INIT_R 9 select BOARD_EARLY_INIT_F 10 11config ARCH_LS1043A 12 bool 13 select ARMV8_SET_SMPEN 14 select FSL_LSCH2 15 select SYS_FSL_DDR 16 select SYS_FSL_DDR_BE 17 select SYS_FSL_DDR_VER_50 18 select SYS_FSL_ERRATUM_A008850 19 select SYS_FSL_ERRATUM_A009660 20 select SYS_FSL_ERRATUM_A009663 21 select SYS_FSL_ERRATUM_A009929 22 select SYS_FSL_ERRATUM_A009942 23 select SYS_FSL_ERRATUM_A010315 24 select SYS_FSL_ERRATUM_A010539 25 select SYS_FSL_HAS_DDR3 26 select SYS_FSL_HAS_DDR4 27 select ARCH_EARLY_INIT_R 28 select BOARD_EARLY_INIT_F 29 imply SCSI 30 imply CMD_PCI 31 32config ARCH_LS1046A 33 bool 34 select ARMV8_SET_SMPEN 35 select FSL_LSCH2 36 select SYS_FSL_DDR 37 select SYS_FSL_DDR_BE 38 select SYS_FSL_DDR_VER_50 39 select SYS_FSL_ERRATUM_A008336 40 select SYS_FSL_ERRATUM_A008511 41 select SYS_FSL_ERRATUM_A008850 42 select SYS_FSL_ERRATUM_A009801 43 select SYS_FSL_ERRATUM_A009803 44 select SYS_FSL_ERRATUM_A009942 45 select SYS_FSL_ERRATUM_A010165 46 select SYS_FSL_ERRATUM_A010539 47 select SYS_FSL_HAS_DDR4 48 select SYS_FSL_SRDS_2 49 select ARCH_EARLY_INIT_R 50 select BOARD_EARLY_INIT_F 51 imply SCSI 52 53config ARCH_LS2080A 54 bool 55 select ARMV8_SET_SMPEN 56 select ARM_ERRATA_826974 57 select ARM_ERRATA_828024 58 select ARM_ERRATA_829520 59 select ARM_ERRATA_833471 60 select FSL_LSCH3 61 select SYS_FSL_DDR 62 select SYS_FSL_DDR_LE 63 select SYS_FSL_DDR_VER_50 64 select SYS_FSL_HAS_DP_DDR 65 select SYS_FSL_HAS_SEC 66 select SYS_FSL_HAS_DDR4 67 select SYS_FSL_SEC_COMPAT_5 68 select SYS_FSL_SEC_LE 69 select SYS_FSL_SRDS_2 70 select FSL_TZASC_1 71 select FSL_TZASC_2 72 select SYS_FSL_ERRATUM_A008336 73 select SYS_FSL_ERRATUM_A008511 74 select SYS_FSL_ERRATUM_A008514 75 select SYS_FSL_ERRATUM_A008585 76 select SYS_FSL_ERRATUM_A009635 77 select SYS_FSL_ERRATUM_A009663 78 select SYS_FSL_ERRATUM_A009801 79 select SYS_FSL_ERRATUM_A009803 80 select SYS_FSL_ERRATUM_A009942 81 select SYS_FSL_ERRATUM_A010165 82 select SYS_FSL_ERRATUM_A009203 83 select ARCH_EARLY_INIT_R 84 select BOARD_EARLY_INIT_F 85 86config FSL_LSCH2 87 bool 88 select SYS_FSL_HAS_SEC 89 select SYS_FSL_SEC_COMPAT_5 90 select SYS_FSL_SEC_BE 91 select SYS_FSL_SRDS_1 92 select SYS_HAS_SERDES 93 94config FSL_LSCH3 95 bool 96 select SYS_FSL_SRDS_1 97 select SYS_HAS_SERDES 98 99config FSL_MC_ENET 100 bool "Management Complex network" 101 depends on ARCH_LS2080A 102 default y 103 select RESV_RAM 104 help 105 Enable Management Complex (MC) network 106 107menu "Layerscape architecture" 108 depends on FSL_LSCH2 || FSL_LSCH3 109 110config FSL_PCIE_COMPAT 111 string "PCIe compatible of Kernel DT" 112 depends on PCIE_LAYERSCAPE 113 default "fsl,ls1012a-pcie" if ARCH_LS1012A 114 default "fsl,ls1043a-pcie" if ARCH_LS1043A 115 default "fsl,ls1046a-pcie" if ARCH_LS1046A 116 default "fsl,ls2080a-pcie" if ARCH_LS2080A 117 help 118 This compatible is used to find pci controller node in Kernel DT 119 to complete fixup. 120 121config HAS_FEATURE_GIC64K_ALIGN 122 bool 123 default y if ARCH_LS1043A 124 125config HAS_FEATURE_ENHANCED_MSI 126 bool 127 default y if ARCH_LS1043A 128 129menu "Layerscape PPA" 130config FSL_LS_PPA 131 bool "FSL Layerscape PPA firmware support" 132 depends on !ARMV8_PSCI 133 select ARMV8_SEC_FIRMWARE_SUPPORT 134 select SEC_FIRMWARE_ARMV8_PSCI 135 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 136 help 137 The FSL Primary Protected Application (PPA) is a software component 138 which is loaded during boot stage, and then remains resident in RAM 139 and runs in the TrustZone after boot. 140 Say y to enable it. 141 142config SPL_FSL_LS_PPA 143 bool "FSL Layerscape PPA firmware support for SPL build" 144 depends on !ARMV8_PSCI 145 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 146 select SEC_FIRMWARE_ARMV8_PSCI 147 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 148 help 149 The FSL Primary Protected Application (PPA) is a software component 150 which is loaded during boot stage, and then remains resident in RAM 151 and runs in the TrustZone after boot. This is to load PPA during SPL 152 stage instead of the RAM version of U-Boot. Once PPA is initialized, 153 the rest of U-Boot (including RAM version) runs at EL2. 154choice 155 prompt "FSL Layerscape PPA firmware loading-media select" 156 depends on FSL_LS_PPA 157 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 158 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 159 default SYS_LS_PPA_FW_IN_XIP 160 161config SYS_LS_PPA_FW_IN_XIP 162 bool "XIP" 163 help 164 Say Y here if the PPA firmware locate at XIP flash, such 165 as NOR or QSPI flash. 166 167config SYS_LS_PPA_FW_IN_MMC 168 bool "eMMC or SD Card" 169 help 170 Say Y here if the PPA firmware locate at eMMC/SD card. 171 172config SYS_LS_PPA_FW_IN_NAND 173 bool "NAND" 174 help 175 Say Y here if the PPA firmware locate at NAND flash. 176 177endchoice 178 179config SYS_LS_PPA_FW_ADDR 180 hex "Address of PPA firmware loading from" 181 depends on FSL_LS_PPA 182 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 183 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 184 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 185 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP 186 default 0x400000 if SYS_LS_PPA_FW_IN_MMC 187 default 0x400000 if SYS_LS_PPA_FW_IN_NAND 188 189 help 190 If the PPA firmware locate at XIP flash, such as NOR or 191 QSPI flash, this address is a directly memory-mapped. 192 If it is in a serial accessed flash, such as NAND and SD 193 card, it is a byte offset. 194 195config SYS_LS_PPA_ESBC_ADDR 196 hex "hdr address of PPA firmware loading from" 197 depends on FSL_LS_PPA && CHAIN_OF_TRUST 198 default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 199 default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 200 default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 201 default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3 202 default 0x700000 if SYS_LS_PPA_FW_IN_MMC 203 default 0x700000 if SYS_LS_PPA_FW_IN_NAND 204 help 205 If the PPA header firmware locate at XIP flash, such as NOR or 206 QSPI flash, this address is a directly memory-mapped. 207 If it is in a serial accessed flash, such as NAND and SD 208 card, it is a byte offset. 209 210config LS_PPA_ESBC_HDR_SIZE 211 hex "Length of PPA ESBC header" 212 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 213 default 0x2000 214 help 215 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 216 NAND to memory to validate PPA image. 217 218endmenu 219 220config SYS_FSL_ERRATUM_A010315 221 bool "Workaround for PCIe erratum A010315" 222 223config SYS_FSL_ERRATUM_A010539 224 bool "Workaround for PIN MUX erratum A010539" 225 226config MAX_CPUS 227 int "Maximum number of CPUs permitted for Layerscape" 228 default 4 if ARCH_LS1043A 229 default 4 if ARCH_LS1046A 230 default 16 if ARCH_LS2080A 231 default 1 232 help 233 Set this number to the maximum number of possible CPUs in the SoC. 234 SoCs may have multiple clusters with each cluster may have multiple 235 ports. If some ports are reserved but higher ports are used for 236 cores, count the reserved ports. This will allocate enough memory 237 in spin table to properly handle all cores. 238 239config SECURE_BOOT 240 bool "Secure Boot" 241 help 242 Enable Freescale Secure Boot feature 243 244config QSPI_AHB_INIT 245 bool "Init the QSPI AHB bus" 246 help 247 The default setting for QSPI AHB bus just support 3bytes addressing. 248 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 249 bus for those flashes to support the full QSPI flash size. 250 251config SYS_FSL_IFC_BANK_COUNT 252 int "Maximum banks of Integrated flash controller" 253 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 254 default 4 if ARCH_LS1043A 255 default 4 if ARCH_LS1046A 256 default 8 if ARCH_LS2080A 257 258config SYS_FSL_HAS_DP_DDR 259 bool 260 261config SYS_FSL_SRDS_1 262 bool 263 264config SYS_FSL_SRDS_2 265 bool 266 267config SYS_HAS_SERDES 268 bool 269 270config FSL_TZASC_1 271 bool 272 273config FSL_TZASC_2 274 bool 275 276endmenu 277 278menu "Layerscape clock tree configuration" 279 depends on FSL_LSCH2 || FSL_LSCH3 280 281config SYS_FSL_CLK 282 bool "Enable clock tree initialization" 283 default y 284 285config CLUSTER_CLK_FREQ 286 int "Reference clock of core cluster" 287 depends on ARCH_LS1012A 288 default 100000000 289 help 290 This number is the reference clock frequency of core PLL. 291 For most platforms, the core PLL and Platform PLL have the same 292 reference clock, but for some platforms, LS1012A for instance, 293 they are provided sepatately. 294 295config SYS_FSL_PCLK_DIV 296 int "Platform clock divider" 297 default 1 if ARCH_LS1043A 298 default 1 if ARCH_LS1046A 299 default 2 300 help 301 This is the divider that is used to derive Platform clock from 302 Platform PLL, in another word: 303 Platform_clk = Platform_PLL_freq / this_divider 304 305config SYS_FSL_DSPI_CLK_DIV 306 int "DSPI clock divider" 307 default 1 if ARCH_LS1043A 308 default 2 309 help 310 This is the divider that is used to derive DSPI clock from Platform 311 clock, in another word DSPI_clk = Platform_clk / this_divider. 312 313config SYS_FSL_DUART_CLK_DIV 314 int "DUART clock divider" 315 default 1 if ARCH_LS1043A 316 default 2 317 help 318 This is the divider that is used to derive DUART clock from Platform 319 clock, in another word DUART_clk = Platform_clk / this_divider. 320 321config SYS_FSL_I2C_CLK_DIV 322 int "I2C clock divider" 323 default 1 if ARCH_LS1043A 324 default 2 325 help 326 This is the divider that is used to derive I2C clock from Platform 327 clock, in another word I2C_clk = Platform_clk / this_divider. 328 329config SYS_FSL_IFC_CLK_DIV 330 int "IFC clock divider" 331 default 1 if ARCH_LS1043A 332 default 2 333 help 334 This is the divider that is used to derive IFC clock from Platform 335 clock, in another word IFC_clk = Platform_clk / this_divider. 336 337config SYS_FSL_LPUART_CLK_DIV 338 int "LPUART clock divider" 339 default 1 if ARCH_LS1043A 340 default 2 341 help 342 This is the divider that is used to derive LPUART clock from Platform 343 clock, in another word LPUART_clk = Platform_clk / this_divider. 344 345config SYS_FSL_SDHC_CLK_DIV 346 int "SDHC clock divider" 347 default 1 if ARCH_LS1043A 348 default 1 if ARCH_LS1012A 349 default 2 350 help 351 This is the divider that is used to derive SDHC clock from Platform 352 clock, in another word SDHC_clk = Platform_clk / this_divider. 353endmenu 354 355config RESV_RAM 356 bool 357 help 358 Reserve memory from the top, tracked by gd->arch.resv_ram. This 359 reserved RAM can be used by special driver that resides in memory 360 after U-Boot exits. It's up to implementation to allocate and allow 361 access to this reserved memory. For example, the reserved RAM can 362 be at the high end of physical memory. The reserve RAM may be 363 excluded from memory bank(s) passed to OS, or marked as reserved. 364 365config SYS_FSL_ERRATUM_A008336 366 bool 367 368config SYS_FSL_ERRATUM_A008514 369 bool 370 371config SYS_FSL_ERRATUM_A008585 372 bool 373 374config SYS_FSL_ERRATUM_A008850 375 bool 376 377config SYS_FSL_ERRATUM_A009203 378 bool 379 380config SYS_FSL_ERRATUM_A009635 381 bool 382 383config SYS_FSL_ERRATUM_A009660 384 bool 385 386config SYS_FSL_ERRATUM_A009929 387 bool 388 389config SYS_MC_RSV_MEM_ALIGN 390 hex "Management Complex reserved memory alignment" 391 depends on RESV_RAM 392 default 0x20000000 393 help 394 Reserved memory needs to be aligned for MC to use. Default value 395 is 512MB. 396