1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 select ARCH_EARLY_INIT_R 9 select BOARD_EARLY_INIT_F 10 11config ARCH_LS1043A 12 bool 13 select ARMV8_SET_SMPEN 14 select FSL_LSCH2 15 select SYS_FSL_DDR 16 select SYS_FSL_DDR_BE 17 select SYS_FSL_DDR_VER_50 18 select SYS_FSL_ERRATUM_A008850 19 select SYS_FSL_ERRATUM_A009660 20 select SYS_FSL_ERRATUM_A009663 21 select SYS_FSL_ERRATUM_A009929 22 select SYS_FSL_ERRATUM_A009942 23 select SYS_FSL_ERRATUM_A010315 24 select SYS_FSL_ERRATUM_A010539 25 select SYS_FSL_HAS_DDR3 26 select SYS_FSL_HAS_DDR4 27 select ARCH_EARLY_INIT_R 28 select BOARD_EARLY_INIT_F 29 30config ARCH_LS1046A 31 bool 32 select ARMV8_SET_SMPEN 33 select FSL_LSCH2 34 select SYS_FSL_DDR 35 select SYS_FSL_DDR_BE 36 select SYS_FSL_DDR_VER_50 37 select SYS_FSL_ERRATUM_A008336 38 select SYS_FSL_ERRATUM_A008511 39 select SYS_FSL_ERRATUM_A009801 40 select SYS_FSL_ERRATUM_A009803 41 select SYS_FSL_ERRATUM_A009942 42 select SYS_FSL_ERRATUM_A010165 43 select SYS_FSL_ERRATUM_A010539 44 select SYS_FSL_HAS_DDR4 45 select SYS_FSL_SRDS_2 46 select ARCH_EARLY_INIT_R 47 select BOARD_EARLY_INIT_F 48 49config ARCH_LS2080A 50 bool 51 select ARMV8_SET_SMPEN 52 select ARM_ERRATA_826974 53 select ARM_ERRATA_828024 54 select ARM_ERRATA_829520 55 select ARM_ERRATA_833471 56 select FSL_LSCH3 57 select SYS_FSL_DDR 58 select SYS_FSL_DDR_LE 59 select SYS_FSL_DDR_VER_50 60 select SYS_FSL_HAS_DP_DDR 61 select SYS_FSL_HAS_SEC 62 select SYS_FSL_HAS_DDR4 63 select SYS_FSL_SEC_COMPAT_5 64 select SYS_FSL_SEC_LE 65 select SYS_FSL_SRDS_2 66 select SYS_FSL_ERRATUM_A008336 67 select SYS_FSL_ERRATUM_A008511 68 select SYS_FSL_ERRATUM_A008514 69 select SYS_FSL_ERRATUM_A008585 70 select SYS_FSL_ERRATUM_A009635 71 select SYS_FSL_ERRATUM_A009663 72 select SYS_FSL_ERRATUM_A009801 73 select SYS_FSL_ERRATUM_A009803 74 select SYS_FSL_ERRATUM_A009942 75 select SYS_FSL_ERRATUM_A010165 76 select SYS_FSL_ERRATUM_A009203 77 select ARCH_EARLY_INIT_R 78 select BOARD_EARLY_INIT_F 79 80config FSL_LSCH2 81 bool 82 select SYS_FSL_HAS_SEC 83 select SYS_FSL_SEC_COMPAT_5 84 select SYS_FSL_SEC_BE 85 select SYS_FSL_SRDS_1 86 select SYS_HAS_SERDES 87 88config FSL_LSCH3 89 bool 90 select SYS_FSL_SRDS_1 91 select SYS_HAS_SERDES 92 93config FSL_MC_ENET 94 bool "Management Complex network" 95 depends on ARCH_LS2080A 96 default y 97 select RESV_RAM 98 help 99 Enable Management Complex (MC) network 100 101menu "Layerscape architecture" 102 depends on FSL_LSCH2 || FSL_LSCH3 103 104config FSL_PCIE_COMPAT 105 string "PCIe compatible of Kernel DT" 106 depends on PCIE_LAYERSCAPE 107 default "fsl,ls1012a-pcie" if ARCH_LS1012A 108 default "fsl,ls1043a-pcie" if ARCH_LS1043A 109 default "fsl,ls1046a-pcie" if ARCH_LS1046A 110 default "fsl,ls2080a-pcie" if ARCH_LS2080A 111 help 112 This compatible is used to find pci controller node in Kernel DT 113 to complete fixup. 114 115config HAS_FEATURE_GIC64K_ALIGN 116 bool 117 default y if ARCH_LS1043A 118 119config HAS_FEATURE_ENHANCED_MSI 120 bool 121 default y if ARCH_LS1043A 122 123menu "Layerscape PPA" 124config FSL_LS_PPA 125 bool "FSL Layerscape PPA firmware support" 126 depends on !ARMV8_PSCI 127 select ARMV8_SEC_FIRMWARE_SUPPORT 128 select SEC_FIRMWARE_ARMV8_PSCI 129 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 130 help 131 The FSL Primary Protected Application (PPA) is a software component 132 which is loaded during boot stage, and then remains resident in RAM 133 and runs in the TrustZone after boot. 134 Say y to enable it. 135choice 136 prompt "FSL Layerscape PPA firmware loading-media select" 137 depends on FSL_LS_PPA 138 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 139 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 140 default SYS_LS_PPA_FW_IN_XIP 141 142config SYS_LS_PPA_FW_IN_XIP 143 bool "XIP" 144 help 145 Say Y here if the PPA firmware locate at XIP flash, such 146 as NOR or QSPI flash. 147 148config SYS_LS_PPA_FW_IN_MMC 149 bool "eMMC or SD Card" 150 help 151 Say Y here if the PPA firmware locate at eMMC/SD card. 152 153config SYS_LS_PPA_FW_IN_NAND 154 bool "NAND" 155 help 156 Say Y here if the PPA firmware locate at NAND flash. 157 158endchoice 159 160config SYS_LS_PPA_FW_ADDR 161 hex "Address of PPA firmware loading from" 162 depends on FSL_LS_PPA 163 default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 164 default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 165 default 0x60500000 if SYS_LS_PPA_FW_IN_XIP 166 default 0x500000 if SYS_LS_PPA_FW_IN_MMC 167 default 0x500000 if SYS_LS_PPA_FW_IN_NAND 168 169 help 170 If the PPA firmware locate at XIP flash, such as NOR or 171 QSPI flash, this address is a directly memory-mapped. 172 If it is in a serial accessed flash, such as NAND and SD 173 card, it is a byte offset. 174endmenu 175 176config SYS_FSL_ERRATUM_A010315 177 bool "Workaround for PCIe erratum A010315" 178 179config SYS_FSL_ERRATUM_A010539 180 bool "Workaround for PIN MUX erratum A010539" 181 182config MAX_CPUS 183 int "Maximum number of CPUs permitted for Layerscape" 184 default 4 if ARCH_LS1043A 185 default 4 if ARCH_LS1046A 186 default 16 if ARCH_LS2080A 187 default 1 188 help 189 Set this number to the maximum number of possible CPUs in the SoC. 190 SoCs may have multiple clusters with each cluster may have multiple 191 ports. If some ports are reserved but higher ports are used for 192 cores, count the reserved ports. This will allocate enough memory 193 in spin table to properly handle all cores. 194 195config SECURE_BOOT 196 bool "Secure Boot" 197 help 198 Enable Freescale Secure Boot feature 199 200config QSPI_AHB_INIT 201 bool "Init the QSPI AHB bus" 202 help 203 The default setting for QSPI AHB bus just support 3bytes addressing. 204 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 205 bus for those flashes to support the full QSPI flash size. 206 207config SYS_FSL_IFC_BANK_COUNT 208 int "Maximum banks of Integrated flash controller" 209 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 210 default 4 if ARCH_LS1043A 211 default 4 if ARCH_LS1046A 212 default 8 if ARCH_LS2080A 213 214config SYS_FSL_HAS_DP_DDR 215 bool 216 217config SYS_FSL_SRDS_1 218 bool 219 220config SYS_FSL_SRDS_2 221 bool 222 223config SYS_HAS_SERDES 224 bool 225 226endmenu 227 228menu "Layerscape clock tree configuration" 229 depends on FSL_LSCH2 || FSL_LSCH3 230 231config SYS_FSL_CLK 232 bool "Enable clock tree initialization" 233 default y 234 235config CLUSTER_CLK_FREQ 236 int "Reference clock of core cluster" 237 depends on ARCH_LS1012A 238 default 100000000 239 help 240 This number is the reference clock frequency of core PLL. 241 For most platforms, the core PLL and Platform PLL have the same 242 reference clock, but for some platforms, LS1012A for instance, 243 they are provided sepatately. 244 245config SYS_FSL_PCLK_DIV 246 int "Platform clock divider" 247 default 1 if ARCH_LS1043A 248 default 1 if ARCH_LS1046A 249 default 2 250 help 251 This is the divider that is used to derive Platform clock from 252 Platform PLL, in another word: 253 Platform_clk = Platform_PLL_freq / this_divider 254 255config SYS_FSL_DSPI_CLK_DIV 256 int "DSPI clock divider" 257 default 1 if ARCH_LS1043A 258 default 2 259 help 260 This is the divider that is used to derive DSPI clock from Platform 261 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. 262 263config SYS_FSL_DUART_CLK_DIV 264 int "DUART clock divider" 265 default 1 if ARCH_LS1043A 266 default 2 267 help 268 This is the divider that is used to derive DUART clock from Platform 269 clock, in another word DUART_clk = Platform_clk / this_divider. 270 271config SYS_FSL_I2C_CLK_DIV 272 int "I2C clock divider" 273 default 1 if ARCH_LS1043A 274 default 2 275 help 276 This is the divider that is used to derive I2C clock from Platform 277 clock, in another word I2C_clk = Platform_clk / this_divider. 278 279config SYS_FSL_IFC_CLK_DIV 280 int "IFC clock divider" 281 default 1 if ARCH_LS1043A 282 default 2 283 help 284 This is the divider that is used to derive IFC clock from Platform 285 clock, in another word IFC_clk = Platform_clk / this_divider. 286 287config SYS_FSL_LPUART_CLK_DIV 288 int "LPUART clock divider" 289 default 1 if ARCH_LS1043A 290 default 2 291 help 292 This is the divider that is used to derive LPUART clock from Platform 293 clock, in another word LPUART_clk = Platform_clk / this_divider. 294 295config SYS_FSL_SDHC_CLK_DIV 296 int "SDHC clock divider" 297 default 1 if ARCH_LS1043A 298 default 1 if ARCH_LS1012A 299 default 2 300 help 301 This is the divider that is used to derive SDHC clock from Platform 302 clock, in another word SDHC_clk = Platform_clk / this_divider. 303endmenu 304 305config RESV_RAM 306 bool 307 help 308 Reserve memory from the top, tracked by gd->arch.resv_ram. This 309 reserved RAM can be used by special driver that resides in memory 310 after U-Boot exits. It's up to implementation to allocate and allow 311 access to this reserved memory. For example, the reserved RAM can 312 be at the high end of physical memory. The reserve RAM may be 313 excluded from memory bank(s) passed to OS, or marked as reserved. 314 315config SYS_FSL_ERRATUM_A008336 316 bool 317 318config SYS_FSL_ERRATUM_A008514 319 bool 320 321config SYS_FSL_ERRATUM_A008585 322 bool 323 324config SYS_FSL_ERRATUM_A008850 325 bool 326 327config SYS_FSL_ERRATUM_A009203 328 bool 329 330config SYS_FSL_ERRATUM_A009635 331 bool 332 333config SYS_FSL_ERRATUM_A009660 334 bool 335 336config SYS_FSL_ERRATUM_A009929 337 bool 338 339config SYS_MC_RSV_MEM_ALIGN 340 hex "Management Complex reserved memory alignment" 341 depends on RESV_RAM 342 default 0x20000000 343 help 344 Reserved memory needs to be aligned for MC to use. Default value 345 is 512MB. 346