1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 select SYS_FSL_ERRATUM_A009798 9 select SYS_FSL_ERRATUM_A008997 10 select SYS_FSL_ERRATUM_A009007 11 select SYS_FSL_ERRATUM_A009008 12 select ARCH_EARLY_INIT_R 13 select BOARD_EARLY_INIT_F 14 15config ARCH_LS1043A 16 bool 17 select ARMV8_SET_SMPEN 18 select FSL_LSCH2 19 select SYS_FSL_DDR 20 select SYS_FSL_DDR_BE 21 select SYS_FSL_DDR_VER_50 22 select SYS_FSL_ERRATUM_A008850 23 select SYS_FSL_ERRATUM_A008997 24 select SYS_FSL_ERRATUM_A009007 25 select SYS_FSL_ERRATUM_A009008 26 select SYS_FSL_ERRATUM_A009660 27 select SYS_FSL_ERRATUM_A009663 28 select SYS_FSL_ERRATUM_A009798 29 select SYS_FSL_ERRATUM_A009929 30 select SYS_FSL_ERRATUM_A009942 31 select SYS_FSL_ERRATUM_A010315 32 select SYS_FSL_ERRATUM_A010539 33 select SYS_FSL_HAS_DDR3 34 select SYS_FSL_HAS_DDR4 35 select ARCH_EARLY_INIT_R 36 select BOARD_EARLY_INIT_F 37 imply SCSI 38 imply CMD_PCI 39 40config ARCH_LS1046A 41 bool 42 select ARMV8_SET_SMPEN 43 select FSL_LSCH2 44 select SYS_FSL_DDR 45 select SYS_FSL_DDR_BE 46 select SYS_FSL_DDR_VER_50 47 select SYS_FSL_ERRATUM_A008336 48 select SYS_FSL_ERRATUM_A008511 49 select SYS_FSL_ERRATUM_A008850 50 select SYS_FSL_ERRATUM_A008997 51 select SYS_FSL_ERRATUM_A009007 52 select SYS_FSL_ERRATUM_A009008 53 select SYS_FSL_ERRATUM_A009798 54 select SYS_FSL_ERRATUM_A009801 55 select SYS_FSL_ERRATUM_A009803 56 select SYS_FSL_ERRATUM_A009942 57 select SYS_FSL_ERRATUM_A010165 58 select SYS_FSL_ERRATUM_A010539 59 select SYS_FSL_HAS_DDR4 60 select SYS_FSL_SRDS_2 61 select ARCH_EARLY_INIT_R 62 select BOARD_EARLY_INIT_F 63 imply SCSI 64 65config ARCH_LS1088A 66 bool 67 select ARMV8_SET_SMPEN 68 select FSL_LSCH3 69 select SYS_FSL_DDR 70 select SYS_FSL_DDR_LE 71 select SYS_FSL_DDR_VER_50 72 select SYS_FSL_EC1 73 select SYS_FSL_EC2 74 select SYS_FSL_ERRATUM_A009803 75 select SYS_FSL_ERRATUM_A009942 76 select SYS_FSL_ERRATUM_A010165 77 select SYS_FSL_ERRATUM_A008511 78 select SYS_FSL_ERRATUM_A008850 79 select SYS_FSL_ERRATUM_A009007 80 select SYS_FSL_HAS_CCI400 81 select SYS_FSL_HAS_DDR4 82 select SYS_FSL_HAS_RGMII 83 select SYS_FSL_HAS_SEC 84 select SYS_FSL_SEC_COMPAT_5 85 select SYS_FSL_SEC_LE 86 select SYS_FSL_SRDS_1 87 select SYS_FSL_SRDS_2 88 select FSL_TZASC_1 89 select ARCH_EARLY_INIT_R 90 select BOARD_EARLY_INIT_F 91 imply SCSI 92 93config ARCH_LS2080A 94 bool 95 select ARMV8_SET_SMPEN 96 select ARM_ERRATA_826974 97 select ARM_ERRATA_828024 98 select ARM_ERRATA_829520 99 select ARM_ERRATA_833471 100 select FSL_LSCH3 101 select SYS_FSL_DDR 102 select SYS_FSL_DDR_LE 103 select SYS_FSL_DDR_VER_50 104 select SYS_FSL_HAS_CCN504 105 select SYS_FSL_HAS_DP_DDR 106 select SYS_FSL_HAS_SEC 107 select SYS_FSL_HAS_DDR4 108 select SYS_FSL_SEC_COMPAT_5 109 select SYS_FSL_SEC_LE 110 select SYS_FSL_SRDS_2 111 select FSL_TZASC_1 112 select FSL_TZASC_2 113 select SYS_FSL_ERRATUM_A008336 114 select SYS_FSL_ERRATUM_A008511 115 select SYS_FSL_ERRATUM_A008514 116 select SYS_FSL_ERRATUM_A008585 117 select SYS_FSL_ERRATUM_A008997 118 select SYS_FSL_ERRATUM_A009007 119 select SYS_FSL_ERRATUM_A009008 120 select SYS_FSL_ERRATUM_A009635 121 select SYS_FSL_ERRATUM_A009663 122 select SYS_FSL_ERRATUM_A009798 123 select SYS_FSL_ERRATUM_A009801 124 select SYS_FSL_ERRATUM_A009803 125 select SYS_FSL_ERRATUM_A009942 126 select SYS_FSL_ERRATUM_A010165 127 select SYS_FSL_ERRATUM_A009203 128 select ARCH_EARLY_INIT_R 129 select BOARD_EARLY_INIT_F 130 131config FSL_LSCH2 132 bool 133 select SYS_FSL_HAS_CCI400 134 select SYS_FSL_HAS_SEC 135 select SYS_FSL_SEC_COMPAT_5 136 select SYS_FSL_SEC_BE 137 select SYS_FSL_SRDS_1 138 select SYS_HAS_SERDES 139 140config FSL_LSCH3 141 bool 142 select SYS_FSL_SRDS_1 143 select SYS_HAS_SERDES 144 145config FSL_MC_ENET 146 bool "Management Complex network" 147 depends on ARCH_LS2080A || ARCH_LS1088A 148 default y 149 select RESV_RAM 150 help 151 Enable Management Complex (MC) network 152 153menu "Layerscape architecture" 154 depends on FSL_LSCH2 || FSL_LSCH3 155 156config FSL_PCIE_COMPAT 157 string "PCIe compatible of Kernel DT" 158 depends on PCIE_LAYERSCAPE 159 default "fsl,ls1012a-pcie" if ARCH_LS1012A 160 default "fsl,ls1043a-pcie" if ARCH_LS1043A 161 default "fsl,ls1046a-pcie" if ARCH_LS1046A 162 default "fsl,ls2080a-pcie" if ARCH_LS2080A 163 default "fsl,ls1088a-pcie" if ARCH_LS1088A 164 help 165 This compatible is used to find pci controller node in Kernel DT 166 to complete fixup. 167 168config HAS_FEATURE_GIC64K_ALIGN 169 bool 170 default y if ARCH_LS1043A 171 172config HAS_FEATURE_ENHANCED_MSI 173 bool 174 default y if ARCH_LS1043A 175 176menu "Layerscape PPA" 177config FSL_LS_PPA 178 bool "FSL Layerscape PPA firmware support" 179 depends on !ARMV8_PSCI 180 select ARMV8_SEC_FIRMWARE_SUPPORT 181 select SEC_FIRMWARE_ARMV8_PSCI 182 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 183 help 184 The FSL Primary Protected Application (PPA) is a software component 185 which is loaded during boot stage, and then remains resident in RAM 186 and runs in the TrustZone after boot. 187 Say y to enable it. 188 189config SPL_FSL_LS_PPA 190 bool "FSL Layerscape PPA firmware support for SPL build" 191 depends on !ARMV8_PSCI 192 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 193 select SEC_FIRMWARE_ARMV8_PSCI 194 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 195 help 196 The FSL Primary Protected Application (PPA) is a software component 197 which is loaded during boot stage, and then remains resident in RAM 198 and runs in the TrustZone after boot. This is to load PPA during SPL 199 stage instead of the RAM version of U-Boot. Once PPA is initialized, 200 the rest of U-Boot (including RAM version) runs at EL2. 201choice 202 prompt "FSL Layerscape PPA firmware loading-media select" 203 depends on FSL_LS_PPA 204 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 205 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 206 default SYS_LS_PPA_FW_IN_XIP 207 208config SYS_LS_PPA_FW_IN_XIP 209 bool "XIP" 210 help 211 Say Y here if the PPA firmware locate at XIP flash, such 212 as NOR or QSPI flash. 213 214config SYS_LS_PPA_FW_IN_MMC 215 bool "eMMC or SD Card" 216 help 217 Say Y here if the PPA firmware locate at eMMC/SD card. 218 219config SYS_LS_PPA_FW_IN_NAND 220 bool "NAND" 221 help 222 Say Y here if the PPA firmware locate at NAND flash. 223 224endchoice 225 226config SYS_LS_PPA_FW_ADDR 227 hex "Address of PPA firmware loading from" 228 depends on FSL_LS_PPA 229 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 230 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 231 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 232 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A 233 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP 234 default 0x400000 if SYS_LS_PPA_FW_IN_MMC 235 default 0x400000 if SYS_LS_PPA_FW_IN_NAND 236 237 help 238 If the PPA firmware locate at XIP flash, such as NOR or 239 QSPI flash, this address is a directly memory-mapped. 240 If it is in a serial accessed flash, such as NAND and SD 241 card, it is a byte offset. 242 243config SYS_LS_PPA_ESBC_ADDR 244 hex "hdr address of PPA firmware loading from" 245 depends on FSL_LS_PPA && CHAIN_OF_TRUST 246 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 247 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 248 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 249 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 250 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 251 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A 252 default 0x680000 if SYS_LS_PPA_FW_IN_MMC 253 default 0x680000 if SYS_LS_PPA_FW_IN_NAND 254 help 255 If the PPA header firmware locate at XIP flash, such as NOR or 256 QSPI flash, this address is a directly memory-mapped. 257 If it is in a serial accessed flash, such as NAND and SD 258 card, it is a byte offset. 259 260config LS_PPA_ESBC_HDR_SIZE 261 hex "Length of PPA ESBC header" 262 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 263 default 0x2000 264 help 265 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 266 NAND to memory to validate PPA image. 267 268endmenu 269 270config SYS_FSL_ERRATUM_A008997 271 bool "Workaround for USB PHY erratum A008997" 272 273config SYS_FSL_ERRATUM_A009007 274 bool 275 help 276 Workaround for USB PHY erratum A009007 277 278config SYS_FSL_ERRATUM_A009008 279 bool "Workaround for USB PHY erratum A009008" 280 281config SYS_FSL_ERRATUM_A009798 282 bool "Workaround for USB PHY erratum A009798" 283 284config SYS_FSL_ERRATUM_A010315 285 bool "Workaround for PCIe erratum A010315" 286 287config SYS_FSL_ERRATUM_A010539 288 bool "Workaround for PIN MUX erratum A010539" 289 290config MAX_CPUS 291 int "Maximum number of CPUs permitted for Layerscape" 292 default 4 if ARCH_LS1043A 293 default 4 if ARCH_LS1046A 294 default 16 if ARCH_LS2080A 295 default 8 if ARCH_LS1088A 296 default 1 297 help 298 Set this number to the maximum number of possible CPUs in the SoC. 299 SoCs may have multiple clusters with each cluster may have multiple 300 ports. If some ports are reserved but higher ports are used for 301 cores, count the reserved ports. This will allocate enough memory 302 in spin table to properly handle all cores. 303 304config SECURE_BOOT 305 bool "Secure Boot" 306 help 307 Enable Freescale Secure Boot feature 308 309config QSPI_AHB_INIT 310 bool "Init the QSPI AHB bus" 311 help 312 The default setting for QSPI AHB bus just support 3bytes addressing. 313 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 314 bus for those flashes to support the full QSPI flash size. 315 316config SYS_CCI400_OFFSET 317 hex "Offset for CCI400 base" 318 depends on SYS_FSL_HAS_CCI400 319 default 0x3090000 if ARCH_LS1088A 320 default 0x180000 if FSL_LSCH2 321 help 322 Offset for CCI400 base 323 CCI400 base addr = CCSRBAR + CCI400_OFFSET 324 325config SYS_FSL_IFC_BANK_COUNT 326 int "Maximum banks of Integrated flash controller" 327 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A 328 default 4 if ARCH_LS1043A 329 default 4 if ARCH_LS1046A 330 default 8 if ARCH_LS2080A || ARCH_LS1088A 331 332config SYS_FSL_HAS_CCI400 333 bool 334 335config SYS_FSL_HAS_CCN504 336 bool 337 338config SYS_FSL_HAS_DP_DDR 339 bool 340 341config SYS_FSL_SRDS_1 342 bool 343 344config SYS_FSL_SRDS_2 345 bool 346 347config SYS_HAS_SERDES 348 bool 349 350config FSL_TZASC_1 351 bool 352 353config FSL_TZASC_2 354 bool 355 356endmenu 357 358menu "Layerscape clock tree configuration" 359 depends on FSL_LSCH2 || FSL_LSCH3 360 361config SYS_FSL_CLK 362 bool "Enable clock tree initialization" 363 default y 364 365config CLUSTER_CLK_FREQ 366 int "Reference clock of core cluster" 367 depends on ARCH_LS1012A 368 default 100000000 369 help 370 This number is the reference clock frequency of core PLL. 371 For most platforms, the core PLL and Platform PLL have the same 372 reference clock, but for some platforms, LS1012A for instance, 373 they are provided sepatately. 374 375config SYS_FSL_PCLK_DIV 376 int "Platform clock divider" 377 default 1 if ARCH_LS1043A 378 default 1 if ARCH_LS1046A 379 default 1 if ARCH_LS1088A 380 default 2 381 help 382 This is the divider that is used to derive Platform clock from 383 Platform PLL, in another word: 384 Platform_clk = Platform_PLL_freq / this_divider 385 386config SYS_FSL_DSPI_CLK_DIV 387 int "DSPI clock divider" 388 default 1 if ARCH_LS1043A 389 default 2 390 help 391 This is the divider that is used to derive DSPI clock from Platform 392 clock, in another word DSPI_clk = Platform_clk / this_divider. 393 394config SYS_FSL_DUART_CLK_DIV 395 int "DUART clock divider" 396 default 1 if ARCH_LS1043A 397 default 2 398 help 399 This is the divider that is used to derive DUART clock from Platform 400 clock, in another word DUART_clk = Platform_clk / this_divider. 401 402config SYS_FSL_I2C_CLK_DIV 403 int "I2C clock divider" 404 default 1 if ARCH_LS1043A 405 default 2 406 help 407 This is the divider that is used to derive I2C clock from Platform 408 clock, in another word I2C_clk = Platform_clk / this_divider. 409 410config SYS_FSL_IFC_CLK_DIV 411 int "IFC clock divider" 412 default 1 if ARCH_LS1043A 413 default 2 414 help 415 This is the divider that is used to derive IFC clock from Platform 416 clock, in another word IFC_clk = Platform_clk / this_divider. 417 418config SYS_FSL_LPUART_CLK_DIV 419 int "LPUART clock divider" 420 default 1 if ARCH_LS1043A 421 default 2 422 help 423 This is the divider that is used to derive LPUART clock from Platform 424 clock, in another word LPUART_clk = Platform_clk / this_divider. 425 426config SYS_FSL_SDHC_CLK_DIV 427 int "SDHC clock divider" 428 default 1 if ARCH_LS1043A 429 default 1 if ARCH_LS1012A 430 default 2 431 help 432 This is the divider that is used to derive SDHC clock from Platform 433 clock, in another word SDHC_clk = Platform_clk / this_divider. 434endmenu 435 436config RESV_RAM 437 bool 438 help 439 Reserve memory from the top, tracked by gd->arch.resv_ram. This 440 reserved RAM can be used by special driver that resides in memory 441 after U-Boot exits. It's up to implementation to allocate and allow 442 access to this reserved memory. For example, the reserved RAM can 443 be at the high end of physical memory. The reserve RAM may be 444 excluded from memory bank(s) passed to OS, or marked as reserved. 445 446config SYS_FSL_EC1 447 bool 448 help 449 Ethernet controller 1, this is connected to MAC3. 450 Provides DPAA2 capabilities 451 452config SYS_FSL_EC2 453 bool 454 help 455 Ethernet controller 2, this is connected to MAC4. 456 Provides DPAA2 capabilities 457 458config SYS_FSL_ERRATUM_A008336 459 bool 460 461config SYS_FSL_ERRATUM_A008514 462 bool 463 464config SYS_FSL_ERRATUM_A008585 465 bool 466 467config SYS_FSL_ERRATUM_A008850 468 bool 469 470config SYS_FSL_ERRATUM_A009203 471 bool 472 473config SYS_FSL_ERRATUM_A009635 474 bool 475 476config SYS_FSL_ERRATUM_A009660 477 bool 478 479config SYS_FSL_ERRATUM_A009929 480 bool 481 482 483config SYS_FSL_HAS_RGMII 484 bool 485 depends on SYS_FSL_EC1 || SYS_FSL_EC2 486 487 488config SYS_MC_RSV_MEM_ALIGN 489 hex "Management Complex reserved memory alignment" 490 depends on RESV_RAM 491 default 0x20000000 if ARCH_LS2080A 492 default 0x70000000 if ARCH_LS1088A 493 help 494 Reserved memory needs to be aligned for MC to use. Default value 495 is 512MB. 496 497config SPL_LDSCRIPT 498 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 499 500config HAS_FSL_XHCI_USB 501 bool 502 default y if ARCH_LS1043A || ARCH_LS1046A 503 help 504 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use 505 pins, select it when the pins are assigned to USB. 506