1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 9config ARCH_LS1043A 10 bool 11 select ARMV8_SET_SMPEN 12 select FSL_LSCH2 13 select SYS_FSL_DDR 14 select SYS_FSL_DDR_BE 15 select SYS_FSL_DDR_VER_50 16 select SYS_FSL_ERRATUM_A008850 17 select SYS_FSL_ERRATUM_A009660 18 select SYS_FSL_ERRATUM_A009663 19 select SYS_FSL_ERRATUM_A009929 20 select SYS_FSL_ERRATUM_A009942 21 select SYS_FSL_ERRATUM_A010315 22 select SYS_FSL_ERRATUM_A010539 23 select SYS_FSL_HAS_DDR3 24 select SYS_FSL_HAS_DDR4 25 26config ARCH_LS1046A 27 bool 28 select ARMV8_SET_SMPEN 29 select FSL_LSCH2 30 select SYS_FSL_DDR 31 select SYS_FSL_DDR_BE 32 select SYS_FSL_DDR_VER_50 33 select SYS_FSL_ERRATUM_A008511 34 select SYS_FSL_ERRATUM_A009801 35 select SYS_FSL_ERRATUM_A009803 36 select SYS_FSL_ERRATUM_A009942 37 select SYS_FSL_ERRATUM_A010165 38 select SYS_FSL_ERRATUM_A010539 39 select SYS_FSL_HAS_DDR4 40 select SYS_FSL_SRDS_2 41 42config ARCH_LS2080A 43 bool 44 select ARMV8_SET_SMPEN 45 select FSL_LSCH3 46 select SYS_FSL_DDR 47 select SYS_FSL_DDR_LE 48 select SYS_FSL_DDR_VER_50 49 select SYS_FSL_HAS_DP_DDR 50 select SYS_FSL_HAS_SEC 51 select SYS_FSL_HAS_DDR4 52 select SYS_FSL_SEC_COMPAT_5 53 select SYS_FSL_SEC_LE 54 select SYS_FSL_SRDS_2 55 select SYS_FSL_ERRATUM_A008336 56 select SYS_FSL_ERRATUM_A008511 57 select SYS_FSL_ERRATUM_A008514 58 select SYS_FSL_ERRATUM_A008585 59 select SYS_FSL_ERRATUM_A009635 60 select SYS_FSL_ERRATUM_A009663 61 select SYS_FSL_ERRATUM_A009801 62 select SYS_FSL_ERRATUM_A009803 63 select SYS_FSL_ERRATUM_A009942 64 select SYS_FSL_ERRATUM_A010165 65 66config FSL_LSCH2 67 bool 68 select SYS_FSL_HAS_SEC 69 select SYS_FSL_SEC_COMPAT_5 70 select SYS_FSL_SEC_BE 71 select SYS_FSL_SRDS_1 72 select SYS_HAS_SERDES 73 74config FSL_LSCH3 75 bool 76 select SYS_FSL_SRDS_1 77 select SYS_HAS_SERDES 78 79menu "Layerscape architecture" 80 depends on FSL_LSCH2 || FSL_LSCH3 81 82config FSL_PCIE_COMPAT 83 string "PCIe compatible of Kernel DT" 84 depends on PCIE_LAYERSCAPE 85 default "fsl,ls1012a-pcie" if ARCH_LS1012A 86 default "fsl,ls1043a-pcie" if ARCH_LS1043A 87 default "fsl,ls1046a-pcie" if ARCH_LS1046A 88 default "fsl,ls2080a-pcie" if ARCH_LS2080A 89 help 90 This compatible is used to find pci controller node in Kernel DT 91 to complete fixup. 92 93config HAS_FEATURE_GIC64K_ALIGN 94 bool 95 default y if ARCH_LS1043A 96 97config HAS_FEATURE_ENHANCED_MSI 98 bool 99 default y if ARCH_LS1043A 100 101menu "Layerscape PPA" 102config FSL_LS_PPA 103 bool "FSL Layerscape PPA firmware support" 104 depends on !ARMV8_PSCI 105 depends on ARCH_LS1043A || ARCH_LS1046A 106 select FSL_PPA_ARMV8_PSCI 107 help 108 The FSL Primary Protected Application (PPA) is a software component 109 which is loaded during boot stage, and then remains resident in RAM 110 and runs in the TrustZone after boot. 111 Say y to enable it. 112 113config FSL_PPA_ARMV8_PSCI 114 bool "PSCI implementation in PPA firmware" 115 depends on FSL_LS_PPA 116 help 117 This config enables the ARMv8 PSCI implementation in PPA firmware. 118 This is a private PSCI implementation and different from those 119 implemented under the common ARMv8 PSCI framework. 120endmenu 121 122config SYS_FSL_ERRATUM_A010315 123 bool "Workaround for PCIe erratum A010315" 124 125config SYS_FSL_ERRATUM_A010539 126 bool "Workaround for PIN MUX erratum A010539" 127 128config MAX_CPUS 129 int "Maximum number of CPUs permitted for Layerscape" 130 default 4 if ARCH_LS1043A 131 default 4 if ARCH_LS1046A 132 default 16 if ARCH_LS2080A 133 default 1 134 help 135 Set this number to the maximum number of possible CPUs in the SoC. 136 SoCs may have multiple clusters with each cluster may have multiple 137 ports. If some ports are reserved but higher ports are used for 138 cores, count the reserved ports. This will allocate enough memory 139 in spin table to properly handle all cores. 140 141config SECURE_BOOT 142 bool "Secure Boot" 143 help 144 Enable Freescale Secure Boot feature 145 146config QSPI_AHB_INIT 147 bool "Init the QSPI AHB bus" 148 help 149 The default setting for QSPI AHB bus just support 3bytes addressing. 150 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 151 bus for those flashes to support the full QSPI flash size. 152 153config SYS_FSL_IFC_BANK_COUNT 154 int "Maximum banks of Integrated flash controller" 155 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 156 default 4 if ARCH_LS1043A 157 default 4 if ARCH_LS1046A 158 default 8 if ARCH_LS2080A 159 160config SYS_FSL_HAS_DP_DDR 161 bool 162 163config SYS_FSL_SRDS_1 164 bool 165 166config SYS_FSL_SRDS_2 167 bool 168 169config SYS_HAS_SERDES 170 bool 171 172endmenu 173 174menu "Layerscape clock tree configuration" 175 depends on FSL_LSCH2 || FSL_LSCH3 176 177config SYS_FSL_CLK 178 bool "Enable clock tree initialization" 179 default y 180 181config CLUSTER_CLK_FREQ 182 int "Reference clock of core cluster" 183 depends on ARCH_LS1012A 184 default 100000000 185 help 186 This number is the reference clock frequency of core PLL. 187 For most platforms, the core PLL and Platform PLL have the same 188 reference clock, but for some platforms, LS1012A for instance, 189 they are provided sepatately. 190 191config SYS_FSL_PCLK_DIV 192 int "Platform clock divider" 193 default 1 if ARCH_LS1043A 194 default 1 if ARCH_LS1046A 195 default 2 196 help 197 This is the divider that is used to derive Platform clock from 198 Platform PLL, in another word: 199 Platform_clk = Platform_PLL_freq / this_divider 200 201config SYS_FSL_DSPI_CLK_DIV 202 int "DSPI clock divider" 203 default 1 if ARCH_LS1043A 204 default 2 205 help 206 This is the divider that is used to derive DSPI clock from Platform 207 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. 208 209config SYS_FSL_DUART_CLK_DIV 210 int "DUART clock divider" 211 default 1 if ARCH_LS1043A 212 default 2 213 help 214 This is the divider that is used to derive DUART clock from Platform 215 clock, in another word DUART_clk = Platform_clk / this_divider. 216 217config SYS_FSL_I2C_CLK_DIV 218 int "I2C clock divider" 219 default 1 if ARCH_LS1043A 220 default 2 221 help 222 This is the divider that is used to derive I2C clock from Platform 223 clock, in another word I2C_clk = Platform_clk / this_divider. 224 225config SYS_FSL_IFC_CLK_DIV 226 int "IFC clock divider" 227 default 1 if ARCH_LS1043A 228 default 2 229 help 230 This is the divider that is used to derive IFC clock from Platform 231 clock, in another word IFC_clk = Platform_clk / this_divider. 232 233config SYS_FSL_LPUART_CLK_DIV 234 int "LPUART clock divider" 235 default 1 if ARCH_LS1043A 236 default 2 237 help 238 This is the divider that is used to derive LPUART clock from Platform 239 clock, in another word LPUART_clk = Platform_clk / this_divider. 240 241config SYS_FSL_SDHC_CLK_DIV 242 int "SDHC clock divider" 243 default 1 if ARCH_LS1043A 244 default 1 if ARCH_LS1012A 245 default 2 246 help 247 This is the divider that is used to derive SDHC clock from Platform 248 clock, in another word SDHC_clk = Platform_clk / this_divider. 249endmenu 250 251config SYS_FSL_ERRATUM_A008336 252 bool 253 254config SYS_FSL_ERRATUM_A008514 255 bool 256 257config SYS_FSL_ERRATUM_A008585 258 bool 259 260config SYS_FSL_ERRATUM_A008850 261 bool 262 263config SYS_FSL_ERRATUM_A009635 264 bool 265 266config SYS_FSL_ERRATUM_A009660 267 bool 268 269config SYS_FSL_ERRATUM_A009929 270 bool 271