1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 select ARCH_EARLY_INIT_R 9 select BOARD_EARLY_INIT_F 10 11config ARCH_LS1043A 12 bool 13 select ARMV8_SET_SMPEN 14 select FSL_LSCH2 15 select SYS_FSL_DDR 16 select SYS_FSL_DDR_BE 17 select SYS_FSL_DDR_VER_50 18 select SYS_FSL_ERRATUM_A008850 19 select SYS_FSL_ERRATUM_A009008 20 select SYS_FSL_ERRATUM_A009660 21 select SYS_FSL_ERRATUM_A009663 22 select SYS_FSL_ERRATUM_A009929 23 select SYS_FSL_ERRATUM_A009942 24 select SYS_FSL_ERRATUM_A010315 25 select SYS_FSL_ERRATUM_A010539 26 select SYS_FSL_HAS_DDR3 27 select SYS_FSL_HAS_DDR4 28 select ARCH_EARLY_INIT_R 29 select BOARD_EARLY_INIT_F 30 imply SCSI 31 imply CMD_PCI 32 33config ARCH_LS1046A 34 bool 35 select ARMV8_SET_SMPEN 36 select FSL_LSCH2 37 select SYS_FSL_DDR 38 select SYS_FSL_DDR_BE 39 select SYS_FSL_DDR_VER_50 40 select SYS_FSL_ERRATUM_A008336 41 select SYS_FSL_ERRATUM_A008511 42 select SYS_FSL_ERRATUM_A008850 43 select SYS_FSL_ERRATUM_A009008 44 select SYS_FSL_ERRATUM_A009801 45 select SYS_FSL_ERRATUM_A009803 46 select SYS_FSL_ERRATUM_A009942 47 select SYS_FSL_ERRATUM_A010165 48 select SYS_FSL_ERRATUM_A010539 49 select SYS_FSL_HAS_DDR4 50 select SYS_FSL_SRDS_2 51 select ARCH_EARLY_INIT_R 52 select BOARD_EARLY_INIT_F 53 imply SCSI 54 55config ARCH_LS1088A 56 bool 57 select ARMV8_SET_SMPEN 58 select FSL_LSCH3 59 select SYS_FSL_DDR 60 select SYS_FSL_DDR_LE 61 select SYS_FSL_DDR_VER_50 62 select SYS_FSL_EC1 63 select SYS_FSL_EC2 64 select SYS_FSL_ERRATUM_A009803 65 select SYS_FSL_ERRATUM_A009942 66 select SYS_FSL_ERRATUM_A010165 67 select SYS_FSL_ERRATUM_A008511 68 select SYS_FSL_ERRATUM_A008850 69 select SYS_FSL_HAS_CCI400 70 select SYS_FSL_HAS_DDR4 71 select SYS_FSL_HAS_RGMII 72 select SYS_FSL_HAS_SEC 73 select SYS_FSL_SEC_COMPAT_5 74 select SYS_FSL_SEC_LE 75 select SYS_FSL_SRDS_1 76 select SYS_FSL_SRDS_2 77 select FSL_TZASC_1 78 select ARCH_EARLY_INIT_R 79 select BOARD_EARLY_INIT_F 80 81config ARCH_LS2080A 82 bool 83 select ARMV8_SET_SMPEN 84 select ARM_ERRATA_826974 85 select ARM_ERRATA_828024 86 select ARM_ERRATA_829520 87 select ARM_ERRATA_833471 88 select FSL_LSCH3 89 select SYS_FSL_DDR 90 select SYS_FSL_DDR_LE 91 select SYS_FSL_DDR_VER_50 92 select SYS_FSL_HAS_CCN504 93 select SYS_FSL_HAS_DP_DDR 94 select SYS_FSL_HAS_SEC 95 select SYS_FSL_HAS_DDR4 96 select SYS_FSL_SEC_COMPAT_5 97 select SYS_FSL_SEC_LE 98 select SYS_FSL_SRDS_2 99 select FSL_TZASC_1 100 select FSL_TZASC_2 101 select SYS_FSL_ERRATUM_A008336 102 select SYS_FSL_ERRATUM_A008511 103 select SYS_FSL_ERRATUM_A008514 104 select SYS_FSL_ERRATUM_A008585 105 select SYS_FSL_ERRATUM_A009008 106 select SYS_FSL_ERRATUM_A009635 107 select SYS_FSL_ERRATUM_A009663 108 select SYS_FSL_ERRATUM_A009801 109 select SYS_FSL_ERRATUM_A009803 110 select SYS_FSL_ERRATUM_A009942 111 select SYS_FSL_ERRATUM_A010165 112 select SYS_FSL_ERRATUM_A009203 113 select ARCH_EARLY_INIT_R 114 select BOARD_EARLY_INIT_F 115 116config FSL_LSCH2 117 bool 118 select SYS_FSL_HAS_CCI400 119 select SYS_FSL_HAS_SEC 120 select SYS_FSL_SEC_COMPAT_5 121 select SYS_FSL_SEC_BE 122 select SYS_FSL_SRDS_1 123 select SYS_HAS_SERDES 124 125config FSL_LSCH3 126 bool 127 select SYS_FSL_SRDS_1 128 select SYS_HAS_SERDES 129 130config FSL_MC_ENET 131 bool "Management Complex network" 132 depends on ARCH_LS2080A || ARCH_LS1088A 133 default y 134 select RESV_RAM 135 help 136 Enable Management Complex (MC) network 137 138menu "Layerscape architecture" 139 depends on FSL_LSCH2 || FSL_LSCH3 140 141config FSL_PCIE_COMPAT 142 string "PCIe compatible of Kernel DT" 143 depends on PCIE_LAYERSCAPE 144 default "fsl,ls1012a-pcie" if ARCH_LS1012A 145 default "fsl,ls1043a-pcie" if ARCH_LS1043A 146 default "fsl,ls1046a-pcie" if ARCH_LS1046A 147 default "fsl,ls2080a-pcie" if ARCH_LS2080A 148 default "fsl,ls1088a-pcie" if ARCH_LS1088A 149 help 150 This compatible is used to find pci controller node in Kernel DT 151 to complete fixup. 152 153config HAS_FEATURE_GIC64K_ALIGN 154 bool 155 default y if ARCH_LS1043A 156 157config HAS_FEATURE_ENHANCED_MSI 158 bool 159 default y if ARCH_LS1043A 160 161menu "Layerscape PPA" 162config FSL_LS_PPA 163 bool "FSL Layerscape PPA firmware support" 164 depends on !ARMV8_PSCI 165 select ARMV8_SEC_FIRMWARE_SUPPORT 166 select SEC_FIRMWARE_ARMV8_PSCI 167 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 168 help 169 The FSL Primary Protected Application (PPA) is a software component 170 which is loaded during boot stage, and then remains resident in RAM 171 and runs in the TrustZone after boot. 172 Say y to enable it. 173 174config SPL_FSL_LS_PPA 175 bool "FSL Layerscape PPA firmware support for SPL build" 176 depends on !ARMV8_PSCI 177 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 178 select SEC_FIRMWARE_ARMV8_PSCI 179 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 180 help 181 The FSL Primary Protected Application (PPA) is a software component 182 which is loaded during boot stage, and then remains resident in RAM 183 and runs in the TrustZone after boot. This is to load PPA during SPL 184 stage instead of the RAM version of U-Boot. Once PPA is initialized, 185 the rest of U-Boot (including RAM version) runs at EL2. 186choice 187 prompt "FSL Layerscape PPA firmware loading-media select" 188 depends on FSL_LS_PPA 189 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 190 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 191 default SYS_LS_PPA_FW_IN_XIP 192 193config SYS_LS_PPA_FW_IN_XIP 194 bool "XIP" 195 help 196 Say Y here if the PPA firmware locate at XIP flash, such 197 as NOR or QSPI flash. 198 199config SYS_LS_PPA_FW_IN_MMC 200 bool "eMMC or SD Card" 201 help 202 Say Y here if the PPA firmware locate at eMMC/SD card. 203 204config SYS_LS_PPA_FW_IN_NAND 205 bool "NAND" 206 help 207 Say Y here if the PPA firmware locate at NAND flash. 208 209endchoice 210 211config SYS_LS_PPA_FW_ADDR 212 hex "Address of PPA firmware loading from" 213 depends on FSL_LS_PPA 214 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 215 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 216 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 217 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A 218 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP 219 default 0x400000 if SYS_LS_PPA_FW_IN_MMC 220 default 0x400000 if SYS_LS_PPA_FW_IN_NAND 221 222 help 223 If the PPA firmware locate at XIP flash, such as NOR or 224 QSPI flash, this address is a directly memory-mapped. 225 If it is in a serial accessed flash, such as NAND and SD 226 card, it is a byte offset. 227 228config SYS_LS_PPA_ESBC_ADDR 229 hex "hdr address of PPA firmware loading from" 230 depends on FSL_LS_PPA && CHAIN_OF_TRUST 231 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 232 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 233 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 234 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 235 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 236 default 0x680000 if SYS_LS_PPA_FW_IN_MMC 237 default 0x680000 if SYS_LS_PPA_FW_IN_NAND 238 help 239 If the PPA header firmware locate at XIP flash, such as NOR or 240 QSPI flash, this address is a directly memory-mapped. 241 If it is in a serial accessed flash, such as NAND and SD 242 card, it is a byte offset. 243 244config LS_PPA_ESBC_HDR_SIZE 245 hex "Length of PPA ESBC header" 246 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 247 default 0x2000 248 help 249 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 250 NAND to memory to validate PPA image. 251 252endmenu 253 254config SYS_FSL_ERRATUM_A009008 255 bool "Workaround for USB PHY erratum A009008" 256 257config SYS_FSL_ERRATUM_A010315 258 bool "Workaround for PCIe erratum A010315" 259 260config SYS_FSL_ERRATUM_A010539 261 bool "Workaround for PIN MUX erratum A010539" 262 263config MAX_CPUS 264 int "Maximum number of CPUs permitted for Layerscape" 265 default 4 if ARCH_LS1043A 266 default 4 if ARCH_LS1046A 267 default 16 if ARCH_LS2080A 268 default 8 if ARCH_LS1088A 269 default 1 270 help 271 Set this number to the maximum number of possible CPUs in the SoC. 272 SoCs may have multiple clusters with each cluster may have multiple 273 ports. If some ports are reserved but higher ports are used for 274 cores, count the reserved ports. This will allocate enough memory 275 in spin table to properly handle all cores. 276 277config SECURE_BOOT 278 bool "Secure Boot" 279 help 280 Enable Freescale Secure Boot feature 281 282config QSPI_AHB_INIT 283 bool "Init the QSPI AHB bus" 284 help 285 The default setting for QSPI AHB bus just support 3bytes addressing. 286 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 287 bus for those flashes to support the full QSPI flash size. 288 289config SYS_CCI400_OFFSET 290 hex "Offset for CCI400 base" 291 depends on SYS_FSL_HAS_CCI400 292 default 0x3090000 if ARCH_LS1088A 293 default 0x180000 if FSL_LSCH2 294 help 295 Offset for CCI400 base 296 CCI400 base addr = CCSRBAR + CCI400_OFFSET 297 298config SYS_FSL_IFC_BANK_COUNT 299 int "Maximum banks of Integrated flash controller" 300 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A 301 default 4 if ARCH_LS1043A 302 default 4 if ARCH_LS1046A 303 default 8 if ARCH_LS2080A || ARCH_LS1088A 304 305config SYS_FSL_HAS_CCI400 306 bool 307 308config SYS_FSL_HAS_CCN504 309 bool 310 311config SYS_FSL_HAS_DP_DDR 312 bool 313 314config SYS_FSL_SRDS_1 315 bool 316 317config SYS_FSL_SRDS_2 318 bool 319 320config SYS_HAS_SERDES 321 bool 322 323config FSL_TZASC_1 324 bool 325 326config FSL_TZASC_2 327 bool 328 329endmenu 330 331menu "Layerscape clock tree configuration" 332 depends on FSL_LSCH2 || FSL_LSCH3 333 334config SYS_FSL_CLK 335 bool "Enable clock tree initialization" 336 default y 337 338config CLUSTER_CLK_FREQ 339 int "Reference clock of core cluster" 340 depends on ARCH_LS1012A 341 default 100000000 342 help 343 This number is the reference clock frequency of core PLL. 344 For most platforms, the core PLL and Platform PLL have the same 345 reference clock, but for some platforms, LS1012A for instance, 346 they are provided sepatately. 347 348config SYS_FSL_PCLK_DIV 349 int "Platform clock divider" 350 default 1 if ARCH_LS1043A 351 default 1 if ARCH_LS1046A 352 default 1 if ARCH_LS1088A 353 default 2 354 help 355 This is the divider that is used to derive Platform clock from 356 Platform PLL, in another word: 357 Platform_clk = Platform_PLL_freq / this_divider 358 359config SYS_FSL_DSPI_CLK_DIV 360 int "DSPI clock divider" 361 default 1 if ARCH_LS1043A 362 default 2 363 help 364 This is the divider that is used to derive DSPI clock from Platform 365 clock, in another word DSPI_clk = Platform_clk / this_divider. 366 367config SYS_FSL_DUART_CLK_DIV 368 int "DUART clock divider" 369 default 1 if ARCH_LS1043A 370 default 2 371 help 372 This is the divider that is used to derive DUART clock from Platform 373 clock, in another word DUART_clk = Platform_clk / this_divider. 374 375config SYS_FSL_I2C_CLK_DIV 376 int "I2C clock divider" 377 default 1 if ARCH_LS1043A 378 default 2 379 help 380 This is the divider that is used to derive I2C clock from Platform 381 clock, in another word I2C_clk = Platform_clk / this_divider. 382 383config SYS_FSL_IFC_CLK_DIV 384 int "IFC clock divider" 385 default 1 if ARCH_LS1043A 386 default 2 387 help 388 This is the divider that is used to derive IFC clock from Platform 389 clock, in another word IFC_clk = Platform_clk / this_divider. 390 391config SYS_FSL_LPUART_CLK_DIV 392 int "LPUART clock divider" 393 default 1 if ARCH_LS1043A 394 default 2 395 help 396 This is the divider that is used to derive LPUART clock from Platform 397 clock, in another word LPUART_clk = Platform_clk / this_divider. 398 399config SYS_FSL_SDHC_CLK_DIV 400 int "SDHC clock divider" 401 default 1 if ARCH_LS1043A 402 default 1 if ARCH_LS1012A 403 default 2 404 help 405 This is the divider that is used to derive SDHC clock from Platform 406 clock, in another word SDHC_clk = Platform_clk / this_divider. 407endmenu 408 409config RESV_RAM 410 bool 411 help 412 Reserve memory from the top, tracked by gd->arch.resv_ram. This 413 reserved RAM can be used by special driver that resides in memory 414 after U-Boot exits. It's up to implementation to allocate and allow 415 access to this reserved memory. For example, the reserved RAM can 416 be at the high end of physical memory. The reserve RAM may be 417 excluded from memory bank(s) passed to OS, or marked as reserved. 418 419config SYS_FSL_EC1 420 bool 421 help 422 Ethernet controller 1, this is connected to MAC3. 423 Provides DPAA2 capabilities 424 425config SYS_FSL_EC2 426 bool 427 help 428 Ethernet controller 2, this is connected to MAC4. 429 Provides DPAA2 capabilities 430 431config SYS_FSL_ERRATUM_A008336 432 bool 433 434config SYS_FSL_ERRATUM_A008514 435 bool 436 437config SYS_FSL_ERRATUM_A008585 438 bool 439 440config SYS_FSL_ERRATUM_A008850 441 bool 442 443config SYS_FSL_ERRATUM_A009203 444 bool 445 446config SYS_FSL_ERRATUM_A009635 447 bool 448 449config SYS_FSL_ERRATUM_A009660 450 bool 451 452config SYS_FSL_ERRATUM_A009929 453 bool 454 455 456config SYS_FSL_HAS_RGMII 457 bool 458 depends on SYS_FSL_EC1 || SYS_FSL_EC2 459 460 461config SYS_MC_RSV_MEM_ALIGN 462 hex "Management Complex reserved memory alignment" 463 depends on RESV_RAM 464 default 0x20000000 if ARCH_LS2080A 465 default 0x70000000 if ARCH_LS1088A 466 help 467 Reserved memory needs to be aligned for MC to use. Default value 468 is 512MB. 469 470config SPL_LDSCRIPT 471 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 472