1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 select ARCH_EARLY_INIT_R 9 select BOARD_EARLY_INIT_F 10 11config ARCH_LS1043A 12 bool 13 select ARMV8_SET_SMPEN 14 select FSL_LSCH2 15 select SYS_FSL_DDR 16 select SYS_FSL_DDR_BE 17 select SYS_FSL_DDR_VER_50 18 select SYS_FSL_ERRATUM_A008850 19 select SYS_FSL_ERRATUM_A008997 20 select SYS_FSL_ERRATUM_A009007 21 select SYS_FSL_ERRATUM_A009008 22 select SYS_FSL_ERRATUM_A009660 23 select SYS_FSL_ERRATUM_A009663 24 select SYS_FSL_ERRATUM_A009798 25 select SYS_FSL_ERRATUM_A009929 26 select SYS_FSL_ERRATUM_A009942 27 select SYS_FSL_ERRATUM_A010315 28 select SYS_FSL_ERRATUM_A010539 29 select SYS_FSL_HAS_DDR3 30 select SYS_FSL_HAS_DDR4 31 select ARCH_EARLY_INIT_R 32 select BOARD_EARLY_INIT_F 33 imply SCSI 34 imply CMD_PCI 35 36config ARCH_LS1046A 37 bool 38 select ARMV8_SET_SMPEN 39 select FSL_LSCH2 40 select SYS_FSL_DDR 41 select SYS_FSL_DDR_BE 42 select SYS_FSL_DDR_VER_50 43 select SYS_FSL_ERRATUM_A008336 44 select SYS_FSL_ERRATUM_A008511 45 select SYS_FSL_ERRATUM_A008850 46 select SYS_FSL_ERRATUM_A008997 47 select SYS_FSL_ERRATUM_A009007 48 select SYS_FSL_ERRATUM_A009008 49 select SYS_FSL_ERRATUM_A009798 50 select SYS_FSL_ERRATUM_A009801 51 select SYS_FSL_ERRATUM_A009803 52 select SYS_FSL_ERRATUM_A009942 53 select SYS_FSL_ERRATUM_A010165 54 select SYS_FSL_ERRATUM_A010539 55 select SYS_FSL_HAS_DDR4 56 select SYS_FSL_SRDS_2 57 select ARCH_EARLY_INIT_R 58 select BOARD_EARLY_INIT_F 59 imply SCSI 60 61config ARCH_LS1088A 62 bool 63 select ARMV8_SET_SMPEN 64 select FSL_LSCH3 65 select SYS_FSL_DDR 66 select SYS_FSL_DDR_LE 67 select SYS_FSL_DDR_VER_50 68 select SYS_FSL_EC1 69 select SYS_FSL_EC2 70 select SYS_FSL_ERRATUM_A009803 71 select SYS_FSL_ERRATUM_A009942 72 select SYS_FSL_ERRATUM_A010165 73 select SYS_FSL_ERRATUM_A008511 74 select SYS_FSL_ERRATUM_A008850 75 select SYS_FSL_HAS_CCI400 76 select SYS_FSL_HAS_DDR4 77 select SYS_FSL_HAS_RGMII 78 select SYS_FSL_HAS_SEC 79 select SYS_FSL_SEC_COMPAT_5 80 select SYS_FSL_SEC_LE 81 select SYS_FSL_SRDS_1 82 select SYS_FSL_SRDS_2 83 select FSL_TZASC_1 84 select ARCH_EARLY_INIT_R 85 select BOARD_EARLY_INIT_F 86 87config ARCH_LS2080A 88 bool 89 select ARMV8_SET_SMPEN 90 select ARM_ERRATA_826974 91 select ARM_ERRATA_828024 92 select ARM_ERRATA_829520 93 select ARM_ERRATA_833471 94 select FSL_LSCH3 95 select SYS_FSL_DDR 96 select SYS_FSL_DDR_LE 97 select SYS_FSL_DDR_VER_50 98 select SYS_FSL_HAS_CCN504 99 select SYS_FSL_HAS_DP_DDR 100 select SYS_FSL_HAS_SEC 101 select SYS_FSL_HAS_DDR4 102 select SYS_FSL_SEC_COMPAT_5 103 select SYS_FSL_SEC_LE 104 select SYS_FSL_SRDS_2 105 select FSL_TZASC_1 106 select FSL_TZASC_2 107 select SYS_FSL_ERRATUM_A008336 108 select SYS_FSL_ERRATUM_A008511 109 select SYS_FSL_ERRATUM_A008514 110 select SYS_FSL_ERRATUM_A008585 111 select SYS_FSL_ERRATUM_A008997 112 select SYS_FSL_ERRATUM_A009007 113 select SYS_FSL_ERRATUM_A009008 114 select SYS_FSL_ERRATUM_A009635 115 select SYS_FSL_ERRATUM_A009663 116 select SYS_FSL_ERRATUM_A009798 117 select SYS_FSL_ERRATUM_A009801 118 select SYS_FSL_ERRATUM_A009803 119 select SYS_FSL_ERRATUM_A009942 120 select SYS_FSL_ERRATUM_A010165 121 select SYS_FSL_ERRATUM_A009203 122 select ARCH_EARLY_INIT_R 123 select BOARD_EARLY_INIT_F 124 125config FSL_LSCH2 126 bool 127 select SYS_FSL_HAS_CCI400 128 select SYS_FSL_HAS_SEC 129 select SYS_FSL_SEC_COMPAT_5 130 select SYS_FSL_SEC_BE 131 select SYS_FSL_SRDS_1 132 select SYS_HAS_SERDES 133 134config FSL_LSCH3 135 bool 136 select SYS_FSL_SRDS_1 137 select SYS_HAS_SERDES 138 139config FSL_MC_ENET 140 bool "Management Complex network" 141 depends on ARCH_LS2080A || ARCH_LS1088A 142 default y 143 select RESV_RAM 144 help 145 Enable Management Complex (MC) network 146 147menu "Layerscape architecture" 148 depends on FSL_LSCH2 || FSL_LSCH3 149 150config FSL_PCIE_COMPAT 151 string "PCIe compatible of Kernel DT" 152 depends on PCIE_LAYERSCAPE 153 default "fsl,ls1012a-pcie" if ARCH_LS1012A 154 default "fsl,ls1043a-pcie" if ARCH_LS1043A 155 default "fsl,ls1046a-pcie" if ARCH_LS1046A 156 default "fsl,ls2080a-pcie" if ARCH_LS2080A 157 default "fsl,ls1088a-pcie" if ARCH_LS1088A 158 help 159 This compatible is used to find pci controller node in Kernel DT 160 to complete fixup. 161 162config HAS_FEATURE_GIC64K_ALIGN 163 bool 164 default y if ARCH_LS1043A 165 166config HAS_FEATURE_ENHANCED_MSI 167 bool 168 default y if ARCH_LS1043A 169 170menu "Layerscape PPA" 171config FSL_LS_PPA 172 bool "FSL Layerscape PPA firmware support" 173 depends on !ARMV8_PSCI 174 select ARMV8_SEC_FIRMWARE_SUPPORT 175 select SEC_FIRMWARE_ARMV8_PSCI 176 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 177 help 178 The FSL Primary Protected Application (PPA) is a software component 179 which is loaded during boot stage, and then remains resident in RAM 180 and runs in the TrustZone after boot. 181 Say y to enable it. 182 183config SPL_FSL_LS_PPA 184 bool "FSL Layerscape PPA firmware support for SPL build" 185 depends on !ARMV8_PSCI 186 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 187 select SEC_FIRMWARE_ARMV8_PSCI 188 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 189 help 190 The FSL Primary Protected Application (PPA) is a software component 191 which is loaded during boot stage, and then remains resident in RAM 192 and runs in the TrustZone after boot. This is to load PPA during SPL 193 stage instead of the RAM version of U-Boot. Once PPA is initialized, 194 the rest of U-Boot (including RAM version) runs at EL2. 195choice 196 prompt "FSL Layerscape PPA firmware loading-media select" 197 depends on FSL_LS_PPA 198 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 199 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 200 default SYS_LS_PPA_FW_IN_XIP 201 202config SYS_LS_PPA_FW_IN_XIP 203 bool "XIP" 204 help 205 Say Y here if the PPA firmware locate at XIP flash, such 206 as NOR or QSPI flash. 207 208config SYS_LS_PPA_FW_IN_MMC 209 bool "eMMC or SD Card" 210 help 211 Say Y here if the PPA firmware locate at eMMC/SD card. 212 213config SYS_LS_PPA_FW_IN_NAND 214 bool "NAND" 215 help 216 Say Y here if the PPA firmware locate at NAND flash. 217 218endchoice 219 220config SYS_LS_PPA_FW_ADDR 221 hex "Address of PPA firmware loading from" 222 depends on FSL_LS_PPA 223 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 224 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 225 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 226 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A 227 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP 228 default 0x400000 if SYS_LS_PPA_FW_IN_MMC 229 default 0x400000 if SYS_LS_PPA_FW_IN_NAND 230 231 help 232 If the PPA firmware locate at XIP flash, such as NOR or 233 QSPI flash, this address is a directly memory-mapped. 234 If it is in a serial accessed flash, such as NAND and SD 235 card, it is a byte offset. 236 237config SYS_LS_PPA_ESBC_ADDR 238 hex "hdr address of PPA firmware loading from" 239 depends on FSL_LS_PPA && CHAIN_OF_TRUST 240 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 241 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 242 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 243 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 244 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 245 default 0x680000 if SYS_LS_PPA_FW_IN_MMC 246 default 0x680000 if SYS_LS_PPA_FW_IN_NAND 247 help 248 If the PPA header firmware locate at XIP flash, such as NOR or 249 QSPI flash, this address is a directly memory-mapped. 250 If it is in a serial accessed flash, such as NAND and SD 251 card, it is a byte offset. 252 253config LS_PPA_ESBC_HDR_SIZE 254 hex "Length of PPA ESBC header" 255 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 256 default 0x2000 257 help 258 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 259 NAND to memory to validate PPA image. 260 261endmenu 262 263config SYS_FSL_ERRATUM_A008997 264 bool "Workaround for USB PHY erratum A008997" 265 266config SYS_FSL_ERRATUM_A009007 267 bool 268 help 269 Workaround for USB PHY erratum A009007 270 271config SYS_FSL_ERRATUM_A009008 272 bool "Workaround for USB PHY erratum A009008" 273 274config SYS_FSL_ERRATUM_A009798 275 bool "Workaround for USB PHY erratum A009798" 276 277config SYS_FSL_ERRATUM_A010315 278 bool "Workaround for PCIe erratum A010315" 279 280config SYS_FSL_ERRATUM_A010539 281 bool "Workaround for PIN MUX erratum A010539" 282 283config MAX_CPUS 284 int "Maximum number of CPUs permitted for Layerscape" 285 default 4 if ARCH_LS1043A 286 default 4 if ARCH_LS1046A 287 default 16 if ARCH_LS2080A 288 default 8 if ARCH_LS1088A 289 default 1 290 help 291 Set this number to the maximum number of possible CPUs in the SoC. 292 SoCs may have multiple clusters with each cluster may have multiple 293 ports. If some ports are reserved but higher ports are used for 294 cores, count the reserved ports. This will allocate enough memory 295 in spin table to properly handle all cores. 296 297config SECURE_BOOT 298 bool "Secure Boot" 299 help 300 Enable Freescale Secure Boot feature 301 302config QSPI_AHB_INIT 303 bool "Init the QSPI AHB bus" 304 help 305 The default setting for QSPI AHB bus just support 3bytes addressing. 306 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 307 bus for those flashes to support the full QSPI flash size. 308 309config SYS_CCI400_OFFSET 310 hex "Offset for CCI400 base" 311 depends on SYS_FSL_HAS_CCI400 312 default 0x3090000 if ARCH_LS1088A 313 default 0x180000 if FSL_LSCH2 314 help 315 Offset for CCI400 base 316 CCI400 base addr = CCSRBAR + CCI400_OFFSET 317 318config SYS_FSL_IFC_BANK_COUNT 319 int "Maximum banks of Integrated flash controller" 320 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A 321 default 4 if ARCH_LS1043A 322 default 4 if ARCH_LS1046A 323 default 8 if ARCH_LS2080A || ARCH_LS1088A 324 325config SYS_FSL_HAS_CCI400 326 bool 327 328config SYS_FSL_HAS_CCN504 329 bool 330 331config SYS_FSL_HAS_DP_DDR 332 bool 333 334config SYS_FSL_SRDS_1 335 bool 336 337config SYS_FSL_SRDS_2 338 bool 339 340config SYS_HAS_SERDES 341 bool 342 343config FSL_TZASC_1 344 bool 345 346config FSL_TZASC_2 347 bool 348 349endmenu 350 351menu "Layerscape clock tree configuration" 352 depends on FSL_LSCH2 || FSL_LSCH3 353 354config SYS_FSL_CLK 355 bool "Enable clock tree initialization" 356 default y 357 358config CLUSTER_CLK_FREQ 359 int "Reference clock of core cluster" 360 depends on ARCH_LS1012A 361 default 100000000 362 help 363 This number is the reference clock frequency of core PLL. 364 For most platforms, the core PLL and Platform PLL have the same 365 reference clock, but for some platforms, LS1012A for instance, 366 they are provided sepatately. 367 368config SYS_FSL_PCLK_DIV 369 int "Platform clock divider" 370 default 1 if ARCH_LS1043A 371 default 1 if ARCH_LS1046A 372 default 1 if ARCH_LS1088A 373 default 2 374 help 375 This is the divider that is used to derive Platform clock from 376 Platform PLL, in another word: 377 Platform_clk = Platform_PLL_freq / this_divider 378 379config SYS_FSL_DSPI_CLK_DIV 380 int "DSPI clock divider" 381 default 1 if ARCH_LS1043A 382 default 2 383 help 384 This is the divider that is used to derive DSPI clock from Platform 385 clock, in another word DSPI_clk = Platform_clk / this_divider. 386 387config SYS_FSL_DUART_CLK_DIV 388 int "DUART clock divider" 389 default 1 if ARCH_LS1043A 390 default 2 391 help 392 This is the divider that is used to derive DUART clock from Platform 393 clock, in another word DUART_clk = Platform_clk / this_divider. 394 395config SYS_FSL_I2C_CLK_DIV 396 int "I2C clock divider" 397 default 1 if ARCH_LS1043A 398 default 2 399 help 400 This is the divider that is used to derive I2C clock from Platform 401 clock, in another word I2C_clk = Platform_clk / this_divider. 402 403config SYS_FSL_IFC_CLK_DIV 404 int "IFC clock divider" 405 default 1 if ARCH_LS1043A 406 default 2 407 help 408 This is the divider that is used to derive IFC clock from Platform 409 clock, in another word IFC_clk = Platform_clk / this_divider. 410 411config SYS_FSL_LPUART_CLK_DIV 412 int "LPUART clock divider" 413 default 1 if ARCH_LS1043A 414 default 2 415 help 416 This is the divider that is used to derive LPUART clock from Platform 417 clock, in another word LPUART_clk = Platform_clk / this_divider. 418 419config SYS_FSL_SDHC_CLK_DIV 420 int "SDHC clock divider" 421 default 1 if ARCH_LS1043A 422 default 1 if ARCH_LS1012A 423 default 2 424 help 425 This is the divider that is used to derive SDHC clock from Platform 426 clock, in another word SDHC_clk = Platform_clk / this_divider. 427endmenu 428 429config RESV_RAM 430 bool 431 help 432 Reserve memory from the top, tracked by gd->arch.resv_ram. This 433 reserved RAM can be used by special driver that resides in memory 434 after U-Boot exits. It's up to implementation to allocate and allow 435 access to this reserved memory. For example, the reserved RAM can 436 be at the high end of physical memory. The reserve RAM may be 437 excluded from memory bank(s) passed to OS, or marked as reserved. 438 439config SYS_FSL_EC1 440 bool 441 help 442 Ethernet controller 1, this is connected to MAC3. 443 Provides DPAA2 capabilities 444 445config SYS_FSL_EC2 446 bool 447 help 448 Ethernet controller 2, this is connected to MAC4. 449 Provides DPAA2 capabilities 450 451config SYS_FSL_ERRATUM_A008336 452 bool 453 454config SYS_FSL_ERRATUM_A008514 455 bool 456 457config SYS_FSL_ERRATUM_A008585 458 bool 459 460config SYS_FSL_ERRATUM_A008850 461 bool 462 463config SYS_FSL_ERRATUM_A009203 464 bool 465 466config SYS_FSL_ERRATUM_A009635 467 bool 468 469config SYS_FSL_ERRATUM_A009660 470 bool 471 472config SYS_FSL_ERRATUM_A009929 473 bool 474 475 476config SYS_FSL_HAS_RGMII 477 bool 478 depends on SYS_FSL_EC1 || SYS_FSL_EC2 479 480 481config SYS_MC_RSV_MEM_ALIGN 482 hex "Management Complex reserved memory alignment" 483 depends on RESV_RAM 484 default 0x20000000 if ARCH_LS2080A 485 default 0x70000000 if ARCH_LS1088A 486 help 487 Reserved memory needs to be aligned for MC to use. Default value 488 is 512MB. 489 490config SPL_LDSCRIPT 491 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 492