1config ARCH_LS1012A 2 bool 3 select FSL_LSCH2 4 select SYS_FSL_DDR_BE 5 select SYS_FSL_MMDC 6 select SYS_FSL_ERRATUM_A010315 7 8config ARCH_LS1043A 9 bool 10 select FSL_LSCH2 11 select SYS_FSL_DDR 12 select SYS_FSL_DDR_BE 13 select SYS_FSL_DDR_VER_50 14 select SYS_FSL_ERRATUM_A008850 15 select SYS_FSL_ERRATUM_A009660 16 select SYS_FSL_ERRATUM_A009663 17 select SYS_FSL_ERRATUM_A009929 18 select SYS_FSL_ERRATUM_A009942 19 select SYS_FSL_ERRATUM_A010315 20 select SYS_FSL_ERRATUM_A010539 21 select SYS_FSL_HAS_DDR3 22 select SYS_FSL_HAS_DDR4 23 24config ARCH_LS1046A 25 bool 26 select FSL_LSCH2 27 select SYS_FSL_DDR 28 select SYS_FSL_DDR_BE 29 select SYS_FSL_DDR_VER_50 30 select SYS_FSL_ERRATUM_A008511 31 select SYS_FSL_ERRATUM_A009801 32 select SYS_FSL_ERRATUM_A009803 33 select SYS_FSL_ERRATUM_A009942 34 select SYS_FSL_ERRATUM_A010165 35 select SYS_FSL_ERRATUM_A010539 36 select SYS_FSL_HAS_DDR4 37 select SYS_FSL_SRDS_2 38 39config ARCH_LS2080A 40 bool 41 select FSL_LSCH3 42 select SYS_FSL_DDR 43 select SYS_FSL_DDR_LE 44 select SYS_FSL_DDR_VER_50 45 select SYS_FSL_HAS_DP_DDR 46 select SYS_FSL_HAS_SEC 47 select SYS_FSL_HAS_DDR4 48 select SYS_FSL_SEC_COMPAT_5 49 select SYS_FSL_SEC_LE 50 select SYS_FSL_SRDS_2 51 select SYS_FSL_ERRATUM_A008336 52 select SYS_FSL_ERRATUM_A008511 53 select SYS_FSL_ERRATUM_A008514 54 select SYS_FSL_ERRATUM_A008585 55 select SYS_FSL_ERRATUM_A009635 56 select SYS_FSL_ERRATUM_A009663 57 select SYS_FSL_ERRATUM_A009801 58 select SYS_FSL_ERRATUM_A009803 59 select SYS_FSL_ERRATUM_A009942 60 select SYS_FSL_ERRATUM_A010165 61 62config FSL_LSCH2 63 bool 64 select SYS_FSL_HAS_SEC 65 select SYS_FSL_SEC_COMPAT_5 66 select SYS_FSL_SEC_BE 67 select SYS_FSL_SRDS_1 68 select SYS_HAS_SERDES 69 70config FSL_LSCH3 71 bool 72 select SYS_FSL_SRDS_1 73 select SYS_HAS_SERDES 74 75menu "Layerscape architecture" 76 depends on FSL_LSCH2 || FSL_LSCH3 77 78config FSL_PCIE_COMPAT 79 string "PCIe compatible of Kernel DT" 80 depends on PCIE_LAYERSCAPE 81 default "fsl,ls1012a-pcie" if ARCH_LS1012A 82 default "fsl,ls1043a-pcie" if ARCH_LS1043A 83 default "fsl,ls1046a-pcie" if ARCH_LS1046A 84 default "fsl,ls2080a-pcie" if ARCH_LS2080A 85 help 86 This compatible is used to find pci controller node in Kernel DT 87 to complete fixup. 88 89menu "Layerscape PPA" 90config FSL_LS_PPA 91 bool "FSL Layerscape PPA firmware support" 92 depends on !ARMV8_PSCI 93 depends on ARCH_LS1043A || ARCH_LS1046A 94 select FSL_PPA_ARMV8_PSCI 95 help 96 The FSL Primary Protected Application (PPA) is a software component 97 which is loaded during boot stage, and then remains resident in RAM 98 and runs in the TrustZone after boot. 99 Say y to enable it. 100 101config FSL_PPA_ARMV8_PSCI 102 bool "PSCI implementation in PPA firmware" 103 depends on FSL_LS_PPA 104 help 105 This config enables the ARMv8 PSCI implementation in PPA firmware. 106 This is a private PSCI implementation and different from those 107 implemented under the common ARMv8 PSCI framework. 108endmenu 109 110config SYS_FSL_ERRATUM_A010315 111 bool "Workaround for PCIe erratum A010315" 112 113config SYS_FSL_ERRATUM_A010539 114 bool "Workaround for PIN MUX erratum A010539" 115 116config MAX_CPUS 117 int "Maximum number of CPUs permitted for Layerscape" 118 default 4 if ARCH_LS1043A 119 default 4 if ARCH_LS1046A 120 default 16 if ARCH_LS2080A 121 default 1 122 help 123 Set this number to the maximum number of possible CPUs in the SoC. 124 SoCs may have multiple clusters with each cluster may have multiple 125 ports. If some ports are reserved but higher ports are used for 126 cores, count the reserved ports. This will allocate enough memory 127 in spin table to properly handle all cores. 128 129config SECURE_BOOT 130 bool 131 help 132 Enable Freescale Secure Boot feature 133 134config QSPI_AHB_INIT 135 bool "Init the QSPI AHB bus" 136 help 137 The default setting for QSPI AHB bus just support 3bytes addressing. 138 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 139 bus for those flashes to support the full QSPI flash size. 140 141config SYS_FSL_IFC_BANK_COUNT 142 int "Maximum banks of Integrated flash controller" 143 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 144 default 4 if ARCH_LS1043A 145 default 4 if ARCH_LS1046A 146 default 8 if ARCH_LS2080A 147 148config SYS_FSL_HAS_DP_DDR 149 bool 150 151config SYS_FSL_SRDS_1 152 bool 153 154config SYS_FSL_SRDS_2 155 bool 156 157config SYS_HAS_SERDES 158 bool 159 160endmenu 161 162config SYS_FSL_ERRATUM_A008336 163 bool 164 165config SYS_FSL_ERRATUM_A008514 166 bool 167 168config SYS_FSL_ERRATUM_A008585 169 bool 170 171config SYS_FSL_ERRATUM_A008850 172 bool 173 174config SYS_FSL_ERRATUM_A009635 175 bool 176 177config SYS_FSL_ERRATUM_A009660 178 bool 179 180config SYS_FSL_ERRATUM_A009929 181 bool 182