1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 select SYS_FSL_ERRATUM_A009798 9 select SYS_FSL_ERRATUM_A008997 10 select SYS_FSL_ERRATUM_A009007 11 select SYS_FSL_ERRATUM_A009008 12 select ARCH_EARLY_INIT_R 13 select BOARD_EARLY_INIT_F 14 15config ARCH_LS1043A 16 bool 17 select ARMV8_SET_SMPEN 18 select FSL_LSCH2 19 select SYS_FSL_DDR 20 select SYS_FSL_DDR_BE 21 select SYS_FSL_DDR_VER_50 22 select SYS_FSL_ERRATUM_A008850 23 select SYS_FSL_ERRATUM_A008997 24 select SYS_FSL_ERRATUM_A009007 25 select SYS_FSL_ERRATUM_A009008 26 select SYS_FSL_ERRATUM_A009660 27 select SYS_FSL_ERRATUM_A009663 28 select SYS_FSL_ERRATUM_A009798 29 select SYS_FSL_ERRATUM_A009929 30 select SYS_FSL_ERRATUM_A009942 31 select SYS_FSL_ERRATUM_A010315 32 select SYS_FSL_ERRATUM_A010539 33 select SYS_FSL_HAS_DDR3 34 select SYS_FSL_HAS_DDR4 35 select ARCH_EARLY_INIT_R 36 select BOARD_EARLY_INIT_F 37 imply SCSI 38 imply SCSI_AHCI 39 imply CMD_PCI 40 41config ARCH_LS1046A 42 bool 43 select ARMV8_SET_SMPEN 44 select FSL_LSCH2 45 select SYS_FSL_DDR 46 select SYS_FSL_DDR_BE 47 select SYS_FSL_DDR_VER_50 48 select SYS_FSL_ERRATUM_A008336 49 select SYS_FSL_ERRATUM_A008511 50 select SYS_FSL_ERRATUM_A008850 51 select SYS_FSL_ERRATUM_A008997 52 select SYS_FSL_ERRATUM_A009007 53 select SYS_FSL_ERRATUM_A009008 54 select SYS_FSL_ERRATUM_A009798 55 select SYS_FSL_ERRATUM_A009801 56 select SYS_FSL_ERRATUM_A009803 57 select SYS_FSL_ERRATUM_A009942 58 select SYS_FSL_ERRATUM_A010165 59 select SYS_FSL_ERRATUM_A010539 60 select SYS_FSL_HAS_DDR4 61 select SYS_FSL_SRDS_2 62 select ARCH_EARLY_INIT_R 63 select BOARD_EARLY_INIT_F 64 imply SCSI 65 imply SCSI_AHCI 66 67config ARCH_LS1088A 68 bool 69 select ARMV8_SET_SMPEN 70 select FSL_LSCH3 71 select SYS_FSL_DDR 72 select SYS_FSL_DDR_LE 73 select SYS_FSL_DDR_VER_50 74 select SYS_FSL_EC1 75 select SYS_FSL_EC2 76 select SYS_FSL_ERRATUM_A009803 77 select SYS_FSL_ERRATUM_A009942 78 select SYS_FSL_ERRATUM_A010165 79 select SYS_FSL_ERRATUM_A008511 80 select SYS_FSL_ERRATUM_A008850 81 select SYS_FSL_ERRATUM_A009007 82 select SYS_FSL_HAS_CCI400 83 select SYS_FSL_HAS_DDR4 84 select SYS_FSL_HAS_RGMII 85 select SYS_FSL_HAS_SEC 86 select SYS_FSL_SEC_COMPAT_5 87 select SYS_FSL_SEC_LE 88 select SYS_FSL_SRDS_1 89 select SYS_FSL_SRDS_2 90 select FSL_TZASC_1 91 select ARCH_EARLY_INIT_R 92 select BOARD_EARLY_INIT_F 93 imply SCSI 94 95config ARCH_LS2080A 96 bool 97 select ARMV8_SET_SMPEN 98 select ARM_ERRATA_826974 99 select ARM_ERRATA_828024 100 select ARM_ERRATA_829520 101 select ARM_ERRATA_833471 102 select FSL_LSCH3 103 select SYS_FSL_DDR 104 select SYS_FSL_DDR_LE 105 select SYS_FSL_DDR_VER_50 106 select SYS_FSL_HAS_CCN504 107 select SYS_FSL_HAS_DP_DDR 108 select SYS_FSL_HAS_SEC 109 select SYS_FSL_HAS_DDR4 110 select SYS_FSL_SEC_COMPAT_5 111 select SYS_FSL_SEC_LE 112 select SYS_FSL_SRDS_2 113 select FSL_TZASC_1 114 select FSL_TZASC_2 115 select SYS_FSL_ERRATUM_A008336 116 select SYS_FSL_ERRATUM_A008511 117 select SYS_FSL_ERRATUM_A008514 118 select SYS_FSL_ERRATUM_A008585 119 select SYS_FSL_ERRATUM_A008997 120 select SYS_FSL_ERRATUM_A009007 121 select SYS_FSL_ERRATUM_A009008 122 select SYS_FSL_ERRATUM_A009635 123 select SYS_FSL_ERRATUM_A009663 124 select SYS_FSL_ERRATUM_A009798 125 select SYS_FSL_ERRATUM_A009801 126 select SYS_FSL_ERRATUM_A009803 127 select SYS_FSL_ERRATUM_A009942 128 select SYS_FSL_ERRATUM_A010165 129 select SYS_FSL_ERRATUM_A009203 130 select ARCH_EARLY_INIT_R 131 select BOARD_EARLY_INIT_F 132 133config FSL_LSCH2 134 bool 135 select SYS_FSL_HAS_CCI400 136 select SYS_FSL_HAS_SEC 137 select SYS_FSL_SEC_COMPAT_5 138 select SYS_FSL_SEC_BE 139 select SYS_FSL_SRDS_1 140 select SYS_HAS_SERDES 141 142config FSL_LSCH3 143 bool 144 select SYS_FSL_SRDS_1 145 select SYS_HAS_SERDES 146 147config FSL_MC_ENET 148 bool "Management Complex network" 149 depends on ARCH_LS2080A || ARCH_LS1088A 150 default y 151 select RESV_RAM 152 help 153 Enable Management Complex (MC) network 154 155menu "Layerscape architecture" 156 depends on FSL_LSCH2 || FSL_LSCH3 157 158config FSL_PCIE_COMPAT 159 string "PCIe compatible of Kernel DT" 160 depends on PCIE_LAYERSCAPE 161 default "fsl,ls1012a-pcie" if ARCH_LS1012A 162 default "fsl,ls1043a-pcie" if ARCH_LS1043A 163 default "fsl,ls1046a-pcie" if ARCH_LS1046A 164 default "fsl,ls2080a-pcie" if ARCH_LS2080A 165 default "fsl,ls1088a-pcie" if ARCH_LS1088A 166 help 167 This compatible is used to find pci controller node in Kernel DT 168 to complete fixup. 169 170config HAS_FEATURE_GIC64K_ALIGN 171 bool 172 default y if ARCH_LS1043A 173 174config HAS_FEATURE_ENHANCED_MSI 175 bool 176 default y if ARCH_LS1043A 177 178menu "Layerscape PPA" 179config FSL_LS_PPA 180 bool "FSL Layerscape PPA firmware support" 181 depends on !ARMV8_PSCI 182 select ARMV8_SEC_FIRMWARE_SUPPORT 183 select SEC_FIRMWARE_ARMV8_PSCI 184 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 185 help 186 The FSL Primary Protected Application (PPA) is a software component 187 which is loaded during boot stage, and then remains resident in RAM 188 and runs in the TrustZone after boot. 189 Say y to enable it. 190 191config SPL_FSL_LS_PPA 192 bool "FSL Layerscape PPA firmware support for SPL build" 193 depends on !ARMV8_PSCI 194 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 195 select SEC_FIRMWARE_ARMV8_PSCI 196 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 197 help 198 The FSL Primary Protected Application (PPA) is a software component 199 which is loaded during boot stage, and then remains resident in RAM 200 and runs in the TrustZone after boot. This is to load PPA during SPL 201 stage instead of the RAM version of U-Boot. Once PPA is initialized, 202 the rest of U-Boot (including RAM version) runs at EL2. 203choice 204 prompt "FSL Layerscape PPA firmware loading-media select" 205 depends on FSL_LS_PPA 206 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 207 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 208 default SYS_LS_PPA_FW_IN_XIP 209 210config SYS_LS_PPA_FW_IN_XIP 211 bool "XIP" 212 help 213 Say Y here if the PPA firmware locate at XIP flash, such 214 as NOR or QSPI flash. 215 216config SYS_LS_PPA_FW_IN_MMC 217 bool "eMMC or SD Card" 218 help 219 Say Y here if the PPA firmware locate at eMMC/SD card. 220 221config SYS_LS_PPA_FW_IN_NAND 222 bool "NAND" 223 help 224 Say Y here if the PPA firmware locate at NAND flash. 225 226endchoice 227 228config SYS_LS_PPA_FW_ADDR 229 hex "Address of PPA firmware loading from" 230 depends on FSL_LS_PPA 231 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 232 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 233 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 234 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A 235 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP 236 default 0x400000 if SYS_LS_PPA_FW_IN_MMC 237 default 0x400000 if SYS_LS_PPA_FW_IN_NAND 238 239 help 240 If the PPA firmware locate at XIP flash, such as NOR or 241 QSPI flash, this address is a directly memory-mapped. 242 If it is in a serial accessed flash, such as NAND and SD 243 card, it is a byte offset. 244 245config SYS_LS_PPA_ESBC_ADDR 246 hex "hdr address of PPA firmware loading from" 247 depends on FSL_LS_PPA && CHAIN_OF_TRUST 248 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 249 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 250 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 251 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 252 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 253 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A 254 default 0x680000 if SYS_LS_PPA_FW_IN_MMC 255 default 0x680000 if SYS_LS_PPA_FW_IN_NAND 256 help 257 If the PPA header firmware locate at XIP flash, such as NOR or 258 QSPI flash, this address is a directly memory-mapped. 259 If it is in a serial accessed flash, such as NAND and SD 260 card, it is a byte offset. 261 262config LS_PPA_ESBC_HDR_SIZE 263 hex "Length of PPA ESBC header" 264 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 265 default 0x2000 266 help 267 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 268 NAND to memory to validate PPA image. 269 270endmenu 271 272config SYS_FSL_ERRATUM_A008997 273 bool "Workaround for USB PHY erratum A008997" 274 275config SYS_FSL_ERRATUM_A009007 276 bool 277 help 278 Workaround for USB PHY erratum A009007 279 280config SYS_FSL_ERRATUM_A009008 281 bool "Workaround for USB PHY erratum A009008" 282 283config SYS_FSL_ERRATUM_A009798 284 bool "Workaround for USB PHY erratum A009798" 285 286config SYS_FSL_ERRATUM_A010315 287 bool "Workaround for PCIe erratum A010315" 288 289config SYS_FSL_ERRATUM_A010539 290 bool "Workaround for PIN MUX erratum A010539" 291 292config MAX_CPUS 293 int "Maximum number of CPUs permitted for Layerscape" 294 default 4 if ARCH_LS1043A 295 default 4 if ARCH_LS1046A 296 default 16 if ARCH_LS2080A 297 default 8 if ARCH_LS1088A 298 default 1 299 help 300 Set this number to the maximum number of possible CPUs in the SoC. 301 SoCs may have multiple clusters with each cluster may have multiple 302 ports. If some ports are reserved but higher ports are used for 303 cores, count the reserved ports. This will allocate enough memory 304 in spin table to properly handle all cores. 305 306config SECURE_BOOT 307 bool "Secure Boot" 308 help 309 Enable Freescale Secure Boot feature 310 311config QSPI_AHB_INIT 312 bool "Init the QSPI AHB bus" 313 help 314 The default setting for QSPI AHB bus just support 3bytes addressing. 315 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 316 bus for those flashes to support the full QSPI flash size. 317 318config SYS_CCI400_OFFSET 319 hex "Offset for CCI400 base" 320 depends on SYS_FSL_HAS_CCI400 321 default 0x3090000 if ARCH_LS1088A 322 default 0x180000 if FSL_LSCH2 323 help 324 Offset for CCI400 base 325 CCI400 base addr = CCSRBAR + CCI400_OFFSET 326 327config SYS_FSL_IFC_BANK_COUNT 328 int "Maximum banks of Integrated flash controller" 329 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A 330 default 4 if ARCH_LS1043A 331 default 4 if ARCH_LS1046A 332 default 8 if ARCH_LS2080A || ARCH_LS1088A 333 334config SYS_FSL_HAS_CCI400 335 bool 336 337config SYS_FSL_HAS_CCN504 338 bool 339 340config SYS_FSL_HAS_DP_DDR 341 bool 342 343config SYS_FSL_SRDS_1 344 bool 345 346config SYS_FSL_SRDS_2 347 bool 348 349config SYS_HAS_SERDES 350 bool 351 352config FSL_TZASC_1 353 bool 354 355config FSL_TZASC_2 356 bool 357 358endmenu 359 360menu "Layerscape clock tree configuration" 361 depends on FSL_LSCH2 || FSL_LSCH3 362 363config SYS_FSL_CLK 364 bool "Enable clock tree initialization" 365 default y 366 367config CLUSTER_CLK_FREQ 368 int "Reference clock of core cluster" 369 depends on ARCH_LS1012A 370 default 100000000 371 help 372 This number is the reference clock frequency of core PLL. 373 For most platforms, the core PLL and Platform PLL have the same 374 reference clock, but for some platforms, LS1012A for instance, 375 they are provided sepatately. 376 377config SYS_FSL_PCLK_DIV 378 int "Platform clock divider" 379 default 1 if ARCH_LS1043A 380 default 1 if ARCH_LS1046A 381 default 1 if ARCH_LS1088A 382 default 2 383 help 384 This is the divider that is used to derive Platform clock from 385 Platform PLL, in another word: 386 Platform_clk = Platform_PLL_freq / this_divider 387 388config SYS_FSL_DSPI_CLK_DIV 389 int "DSPI clock divider" 390 default 1 if ARCH_LS1043A 391 default 2 392 help 393 This is the divider that is used to derive DSPI clock from Platform 394 clock, in another word DSPI_clk = Platform_clk / this_divider. 395 396config SYS_FSL_DUART_CLK_DIV 397 int "DUART clock divider" 398 default 1 if ARCH_LS1043A 399 default 2 400 help 401 This is the divider that is used to derive DUART clock from Platform 402 clock, in another word DUART_clk = Platform_clk / this_divider. 403 404config SYS_FSL_I2C_CLK_DIV 405 int "I2C clock divider" 406 default 1 if ARCH_LS1043A 407 default 2 408 help 409 This is the divider that is used to derive I2C clock from Platform 410 clock, in another word I2C_clk = Platform_clk / this_divider. 411 412config SYS_FSL_IFC_CLK_DIV 413 int "IFC clock divider" 414 default 1 if ARCH_LS1043A 415 default 2 416 help 417 This is the divider that is used to derive IFC clock from Platform 418 clock, in another word IFC_clk = Platform_clk / this_divider. 419 420config SYS_FSL_LPUART_CLK_DIV 421 int "LPUART clock divider" 422 default 1 if ARCH_LS1043A 423 default 2 424 help 425 This is the divider that is used to derive LPUART clock from Platform 426 clock, in another word LPUART_clk = Platform_clk / this_divider. 427 428config SYS_FSL_SDHC_CLK_DIV 429 int "SDHC clock divider" 430 default 1 if ARCH_LS1043A 431 default 1 if ARCH_LS1012A 432 default 2 433 help 434 This is the divider that is used to derive SDHC clock from Platform 435 clock, in another word SDHC_clk = Platform_clk / this_divider. 436endmenu 437 438config RESV_RAM 439 bool 440 help 441 Reserve memory from the top, tracked by gd->arch.resv_ram. This 442 reserved RAM can be used by special driver that resides in memory 443 after U-Boot exits. It's up to implementation to allocate and allow 444 access to this reserved memory. For example, the reserved RAM can 445 be at the high end of physical memory. The reserve RAM may be 446 excluded from memory bank(s) passed to OS, or marked as reserved. 447 448config SYS_FSL_EC1 449 bool 450 help 451 Ethernet controller 1, this is connected to MAC3. 452 Provides DPAA2 capabilities 453 454config SYS_FSL_EC2 455 bool 456 help 457 Ethernet controller 2, this is connected to MAC4. 458 Provides DPAA2 capabilities 459 460config SYS_FSL_ERRATUM_A008336 461 bool 462 463config SYS_FSL_ERRATUM_A008514 464 bool 465 466config SYS_FSL_ERRATUM_A008585 467 bool 468 469config SYS_FSL_ERRATUM_A008850 470 bool 471 472config SYS_FSL_ERRATUM_A009203 473 bool 474 475config SYS_FSL_ERRATUM_A009635 476 bool 477 478config SYS_FSL_ERRATUM_A009660 479 bool 480 481config SYS_FSL_ERRATUM_A009929 482 bool 483 484 485config SYS_FSL_HAS_RGMII 486 bool 487 depends on SYS_FSL_EC1 || SYS_FSL_EC2 488 489 490config SYS_MC_RSV_MEM_ALIGN 491 hex "Management Complex reserved memory alignment" 492 depends on RESV_RAM 493 default 0x20000000 if ARCH_LS2080A 494 default 0x70000000 if ARCH_LS1088A 495 help 496 Reserved memory needs to be aligned for MC to use. Default value 497 is 512MB. 498 499config SPL_LDSCRIPT 500 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 501 502config HAS_FSL_XHCI_USB 503 bool 504 default y if ARCH_LS1043A || ARCH_LS1046A 505 help 506 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use 507 pins, select it when the pins are assigned to USB. 508