1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 select ARCH_EARLY_INIT_R 9 select BOARD_EARLY_INIT_F 10 11config ARCH_LS1043A 12 bool 13 select ARMV8_SET_SMPEN 14 select FSL_LSCH2 15 select SYS_FSL_DDR 16 select SYS_FSL_DDR_BE 17 select SYS_FSL_DDR_VER_50 18 select SYS_FSL_ERRATUM_A008850 19 select SYS_FSL_ERRATUM_A009660 20 select SYS_FSL_ERRATUM_A009663 21 select SYS_FSL_ERRATUM_A009929 22 select SYS_FSL_ERRATUM_A009942 23 select SYS_FSL_ERRATUM_A010315 24 select SYS_FSL_ERRATUM_A010539 25 select SYS_FSL_HAS_DDR3 26 select SYS_FSL_HAS_DDR4 27 select ARCH_EARLY_INIT_R 28 select BOARD_EARLY_INIT_F 29 30config ARCH_LS1046A 31 bool 32 select ARMV8_SET_SMPEN 33 select FSL_LSCH2 34 select SYS_FSL_DDR 35 select SYS_FSL_DDR_BE 36 select SYS_FSL_DDR_VER_50 37 select SYS_FSL_ERRATUM_A008336 38 select SYS_FSL_ERRATUM_A008511 39 select SYS_FSL_ERRATUM_A009801 40 select SYS_FSL_ERRATUM_A009803 41 select SYS_FSL_ERRATUM_A009942 42 select SYS_FSL_ERRATUM_A010165 43 select SYS_FSL_ERRATUM_A010539 44 select SYS_FSL_HAS_DDR4 45 select SYS_FSL_SRDS_2 46 select ARCH_EARLY_INIT_R 47 select BOARD_EARLY_INIT_F 48 49config ARCH_LS2080A 50 bool 51 select ARMV8_SET_SMPEN 52 select FSL_LSCH3 53 select SYS_FSL_DDR 54 select SYS_FSL_DDR_LE 55 select SYS_FSL_DDR_VER_50 56 select SYS_FSL_HAS_DP_DDR 57 select SYS_FSL_HAS_SEC 58 select SYS_FSL_HAS_DDR4 59 select SYS_FSL_SEC_COMPAT_5 60 select SYS_FSL_SEC_LE 61 select SYS_FSL_SRDS_2 62 select SYS_FSL_ERRATUM_A008336 63 select SYS_FSL_ERRATUM_A008511 64 select SYS_FSL_ERRATUM_A008514 65 select SYS_FSL_ERRATUM_A008585 66 select SYS_FSL_ERRATUM_A009635 67 select SYS_FSL_ERRATUM_A009663 68 select SYS_FSL_ERRATUM_A009801 69 select SYS_FSL_ERRATUM_A009803 70 select SYS_FSL_ERRATUM_A009942 71 select SYS_FSL_ERRATUM_A010165 72 select ARCH_EARLY_INIT_R 73 select BOARD_EARLY_INIT_F 74 75config FSL_LSCH2 76 bool 77 select SYS_FSL_HAS_SEC 78 select SYS_FSL_SEC_COMPAT_5 79 select SYS_FSL_SEC_BE 80 select SYS_FSL_SRDS_1 81 select SYS_HAS_SERDES 82 83config FSL_LSCH3 84 bool 85 select SYS_FSL_SRDS_1 86 select SYS_HAS_SERDES 87 88menu "Layerscape architecture" 89 depends on FSL_LSCH2 || FSL_LSCH3 90 91config FSL_PCIE_COMPAT 92 string "PCIe compatible of Kernel DT" 93 depends on PCIE_LAYERSCAPE 94 default "fsl,ls1012a-pcie" if ARCH_LS1012A 95 default "fsl,ls1043a-pcie" if ARCH_LS1043A 96 default "fsl,ls1046a-pcie" if ARCH_LS1046A 97 default "fsl,ls2080a-pcie" if ARCH_LS2080A 98 help 99 This compatible is used to find pci controller node in Kernel DT 100 to complete fixup. 101 102config HAS_FEATURE_GIC64K_ALIGN 103 bool 104 default y if ARCH_LS1043A 105 106config HAS_FEATURE_ENHANCED_MSI 107 bool 108 default y if ARCH_LS1043A 109 110menu "Layerscape PPA" 111config FSL_LS_PPA 112 bool "FSL Layerscape PPA firmware support" 113 depends on !ARMV8_PSCI 114 select ARMV8_SEC_FIRMWARE_SUPPORT 115 select SEC_FIRMWARE_ARMV8_PSCI 116 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 117 help 118 The FSL Primary Protected Application (PPA) is a software component 119 which is loaded during boot stage, and then remains resident in RAM 120 and runs in the TrustZone after boot. 121 Say y to enable it. 122choice 123 prompt "FSL Layerscape PPA firmware loading-media select" 124 depends on FSL_LS_PPA 125 default SYS_LS_PPA_FW_IN_XIP 126 127config SYS_LS_PPA_FW_IN_XIP 128 bool "XIP" 129 help 130 Say Y here if the PPA firmware locate at XIP flash, such 131 as NOR or QSPI flash. 132 133endchoice 134 135config SYS_LS_PPA_FW_ADDR 136 hex "Address of PPA firmware loading from" 137 depends on FSL_LS_PPA 138 default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 139 default 0x60500000 if SYS_LS_PPA_FW_IN_XIP 140 help 141 If the PPA firmware locate at XIP flash, such as NOR or 142 QSPI flash, this address is a directly memory-mapped. 143 If it is in a serial accessed flash, such as NAND and SD 144 card, it is a byte offset. 145endmenu 146 147config SYS_FSL_ERRATUM_A010315 148 bool "Workaround for PCIe erratum A010315" 149 150config SYS_FSL_ERRATUM_A010539 151 bool "Workaround for PIN MUX erratum A010539" 152 153config MAX_CPUS 154 int "Maximum number of CPUs permitted for Layerscape" 155 default 4 if ARCH_LS1043A 156 default 4 if ARCH_LS1046A 157 default 16 if ARCH_LS2080A 158 default 1 159 help 160 Set this number to the maximum number of possible CPUs in the SoC. 161 SoCs may have multiple clusters with each cluster may have multiple 162 ports. If some ports are reserved but higher ports are used for 163 cores, count the reserved ports. This will allocate enough memory 164 in spin table to properly handle all cores. 165 166config SECURE_BOOT 167 bool "Secure Boot" 168 help 169 Enable Freescale Secure Boot feature 170 171config QSPI_AHB_INIT 172 bool "Init the QSPI AHB bus" 173 help 174 The default setting for QSPI AHB bus just support 3bytes addressing. 175 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 176 bus for those flashes to support the full QSPI flash size. 177 178config SYS_FSL_IFC_BANK_COUNT 179 int "Maximum banks of Integrated flash controller" 180 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 181 default 4 if ARCH_LS1043A 182 default 4 if ARCH_LS1046A 183 default 8 if ARCH_LS2080A 184 185config SYS_FSL_HAS_DP_DDR 186 bool 187 188config SYS_FSL_SRDS_1 189 bool 190 191config SYS_FSL_SRDS_2 192 bool 193 194config SYS_HAS_SERDES 195 bool 196 197endmenu 198 199menu "Layerscape clock tree configuration" 200 depends on FSL_LSCH2 || FSL_LSCH3 201 202config SYS_FSL_CLK 203 bool "Enable clock tree initialization" 204 default y 205 206config CLUSTER_CLK_FREQ 207 int "Reference clock of core cluster" 208 depends on ARCH_LS1012A 209 default 100000000 210 help 211 This number is the reference clock frequency of core PLL. 212 For most platforms, the core PLL and Platform PLL have the same 213 reference clock, but for some platforms, LS1012A for instance, 214 they are provided sepatately. 215 216config SYS_FSL_PCLK_DIV 217 int "Platform clock divider" 218 default 1 if ARCH_LS1043A 219 default 1 if ARCH_LS1046A 220 default 2 221 help 222 This is the divider that is used to derive Platform clock from 223 Platform PLL, in another word: 224 Platform_clk = Platform_PLL_freq / this_divider 225 226config SYS_FSL_DSPI_CLK_DIV 227 int "DSPI clock divider" 228 default 1 if ARCH_LS1043A 229 default 2 230 help 231 This is the divider that is used to derive DSPI clock from Platform 232 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. 233 234config SYS_FSL_DUART_CLK_DIV 235 int "DUART clock divider" 236 default 1 if ARCH_LS1043A 237 default 2 238 help 239 This is the divider that is used to derive DUART clock from Platform 240 clock, in another word DUART_clk = Platform_clk / this_divider. 241 242config SYS_FSL_I2C_CLK_DIV 243 int "I2C clock divider" 244 default 1 if ARCH_LS1043A 245 default 2 246 help 247 This is the divider that is used to derive I2C clock from Platform 248 clock, in another word I2C_clk = Platform_clk / this_divider. 249 250config SYS_FSL_IFC_CLK_DIV 251 int "IFC clock divider" 252 default 1 if ARCH_LS1043A 253 default 2 254 help 255 This is the divider that is used to derive IFC clock from Platform 256 clock, in another word IFC_clk = Platform_clk / this_divider. 257 258config SYS_FSL_LPUART_CLK_DIV 259 int "LPUART clock divider" 260 default 1 if ARCH_LS1043A 261 default 2 262 help 263 This is the divider that is used to derive LPUART clock from Platform 264 clock, in another word LPUART_clk = Platform_clk / this_divider. 265 266config SYS_FSL_SDHC_CLK_DIV 267 int "SDHC clock divider" 268 default 1 if ARCH_LS1043A 269 default 1 if ARCH_LS1012A 270 default 2 271 help 272 This is the divider that is used to derive SDHC clock from Platform 273 clock, in another word SDHC_clk = Platform_clk / this_divider. 274endmenu 275 276config SYS_FSL_ERRATUM_A008336 277 bool 278 279config SYS_FSL_ERRATUM_A008514 280 bool 281 282config SYS_FSL_ERRATUM_A008585 283 bool 284 285config SYS_FSL_ERRATUM_A008850 286 bool 287 288config SYS_FSL_ERRATUM_A009635 289 bool 290 291config SYS_FSL_ERRATUM_A009660 292 bool 293 294config SYS_FSL_ERRATUM_A009929 295 bool 296