1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 select ARCH_EARLY_INIT_R 9 select BOARD_EARLY_INIT_F 10 11config ARCH_LS1043A 12 bool 13 select ARMV8_SET_SMPEN 14 select FSL_LSCH2 15 select SYS_FSL_DDR 16 select SYS_FSL_DDR_BE 17 select SYS_FSL_DDR_VER_50 18 select SYS_FSL_ERRATUM_A008850 19 select SYS_FSL_ERRATUM_A009660 20 select SYS_FSL_ERRATUM_A009663 21 select SYS_FSL_ERRATUM_A009929 22 select SYS_FSL_ERRATUM_A009942 23 select SYS_FSL_ERRATUM_A010315 24 select SYS_FSL_ERRATUM_A010539 25 select SYS_FSL_HAS_DDR3 26 select SYS_FSL_HAS_DDR4 27 select ARCH_EARLY_INIT_R 28 select BOARD_EARLY_INIT_F 29 imply SCSI 30 imply CMD_PCI 31 32config ARCH_LS1046A 33 bool 34 select ARMV8_SET_SMPEN 35 select FSL_LSCH2 36 select SYS_FSL_DDR 37 select SYS_FSL_DDR_BE 38 select SYS_FSL_DDR_VER_50 39 select SYS_FSL_ERRATUM_A008336 40 select SYS_FSL_ERRATUM_A008511 41 select SYS_FSL_ERRATUM_A008850 42 select SYS_FSL_ERRATUM_A009801 43 select SYS_FSL_ERRATUM_A009803 44 select SYS_FSL_ERRATUM_A009942 45 select SYS_FSL_ERRATUM_A010165 46 select SYS_FSL_ERRATUM_A010539 47 select SYS_FSL_HAS_DDR4 48 select SYS_FSL_SRDS_2 49 select ARCH_EARLY_INIT_R 50 select BOARD_EARLY_INIT_F 51 imply SCSI 52 53config ARCH_LS2080A 54 bool 55 select ARMV8_SET_SMPEN 56 select ARM_ERRATA_826974 57 select ARM_ERRATA_828024 58 select ARM_ERRATA_829520 59 select ARM_ERRATA_833471 60 select FSL_LSCH3 61 select SYS_FSL_DDR 62 select SYS_FSL_DDR_LE 63 select SYS_FSL_DDR_VER_50 64 select SYS_FSL_HAS_DP_DDR 65 select SYS_FSL_HAS_SEC 66 select SYS_FSL_HAS_DDR4 67 select SYS_FSL_SEC_COMPAT_5 68 select SYS_FSL_SEC_LE 69 select SYS_FSL_SRDS_2 70 select FSL_TZASC_1 71 select FSL_TZASC_2 72 select SYS_FSL_ERRATUM_A008336 73 select SYS_FSL_ERRATUM_A008511 74 select SYS_FSL_ERRATUM_A008514 75 select SYS_FSL_ERRATUM_A008585 76 select SYS_FSL_ERRATUM_A009635 77 select SYS_FSL_ERRATUM_A009663 78 select SYS_FSL_ERRATUM_A009801 79 select SYS_FSL_ERRATUM_A009803 80 select SYS_FSL_ERRATUM_A009942 81 select SYS_FSL_ERRATUM_A010165 82 select SYS_FSL_ERRATUM_A009203 83 select ARCH_EARLY_INIT_R 84 select BOARD_EARLY_INIT_F 85 86config FSL_LSCH2 87 bool 88 select SYS_FSL_HAS_CCI400 89 select SYS_FSL_HAS_SEC 90 select SYS_FSL_SEC_COMPAT_5 91 select SYS_FSL_SEC_BE 92 select SYS_FSL_SRDS_1 93 select SYS_HAS_SERDES 94 95config FSL_LSCH3 96 bool 97 select SYS_FSL_SRDS_1 98 select SYS_HAS_SERDES 99 100config FSL_MC_ENET 101 bool "Management Complex network" 102 depends on ARCH_LS2080A 103 default y 104 select RESV_RAM 105 help 106 Enable Management Complex (MC) network 107 108menu "Layerscape architecture" 109 depends on FSL_LSCH2 || FSL_LSCH3 110 111config FSL_PCIE_COMPAT 112 string "PCIe compatible of Kernel DT" 113 depends on PCIE_LAYERSCAPE 114 default "fsl,ls1012a-pcie" if ARCH_LS1012A 115 default "fsl,ls1043a-pcie" if ARCH_LS1043A 116 default "fsl,ls1046a-pcie" if ARCH_LS1046A 117 default "fsl,ls2080a-pcie" if ARCH_LS2080A 118 help 119 This compatible is used to find pci controller node in Kernel DT 120 to complete fixup. 121 122config HAS_FEATURE_GIC64K_ALIGN 123 bool 124 default y if ARCH_LS1043A 125 126config HAS_FEATURE_ENHANCED_MSI 127 bool 128 default y if ARCH_LS1043A 129 130menu "Layerscape PPA" 131config FSL_LS_PPA 132 bool "FSL Layerscape PPA firmware support" 133 depends on !ARMV8_PSCI 134 select ARMV8_SEC_FIRMWARE_SUPPORT 135 select SEC_FIRMWARE_ARMV8_PSCI 136 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 137 help 138 The FSL Primary Protected Application (PPA) is a software component 139 which is loaded during boot stage, and then remains resident in RAM 140 and runs in the TrustZone after boot. 141 Say y to enable it. 142 143config SPL_FSL_LS_PPA 144 bool "FSL Layerscape PPA firmware support for SPL build" 145 depends on !ARMV8_PSCI 146 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 147 select SEC_FIRMWARE_ARMV8_PSCI 148 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 149 help 150 The FSL Primary Protected Application (PPA) is a software component 151 which is loaded during boot stage, and then remains resident in RAM 152 and runs in the TrustZone after boot. This is to load PPA during SPL 153 stage instead of the RAM version of U-Boot. Once PPA is initialized, 154 the rest of U-Boot (including RAM version) runs at EL2. 155choice 156 prompt "FSL Layerscape PPA firmware loading-media select" 157 depends on FSL_LS_PPA 158 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 159 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 160 default SYS_LS_PPA_FW_IN_XIP 161 162config SYS_LS_PPA_FW_IN_XIP 163 bool "XIP" 164 help 165 Say Y here if the PPA firmware locate at XIP flash, such 166 as NOR or QSPI flash. 167 168config SYS_LS_PPA_FW_IN_MMC 169 bool "eMMC or SD Card" 170 help 171 Say Y here if the PPA firmware locate at eMMC/SD card. 172 173config SYS_LS_PPA_FW_IN_NAND 174 bool "NAND" 175 help 176 Say Y here if the PPA firmware locate at NAND flash. 177 178endchoice 179 180config SYS_LS_PPA_FW_ADDR 181 hex "Address of PPA firmware loading from" 182 depends on FSL_LS_PPA 183 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A 184 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 185 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A 186 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP 187 default 0x400000 if SYS_LS_PPA_FW_IN_MMC 188 default 0x400000 if SYS_LS_PPA_FW_IN_NAND 189 190 help 191 If the PPA firmware locate at XIP flash, such as NOR or 192 QSPI flash, this address is a directly memory-mapped. 193 If it is in a serial accessed flash, such as NAND and SD 194 card, it is a byte offset. 195 196config SYS_LS_PPA_ESBC_ADDR 197 hex "hdr address of PPA firmware loading from" 198 depends on FSL_LS_PPA && CHAIN_OF_TRUST 199 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A 200 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A 201 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A 202 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3 203 default 0x680000 if SYS_LS_PPA_FW_IN_MMC 204 default 0x680000 if SYS_LS_PPA_FW_IN_NAND 205 help 206 If the PPA header firmware locate at XIP flash, such as NOR or 207 QSPI flash, this address is a directly memory-mapped. 208 If it is in a serial accessed flash, such as NAND and SD 209 card, it is a byte offset. 210 211config LS_PPA_ESBC_HDR_SIZE 212 hex "Length of PPA ESBC header" 213 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 214 default 0x2000 215 help 216 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 217 NAND to memory to validate PPA image. 218 219endmenu 220 221config SYS_FSL_ERRATUM_A010315 222 bool "Workaround for PCIe erratum A010315" 223 224config SYS_FSL_ERRATUM_A010539 225 bool "Workaround for PIN MUX erratum A010539" 226 227config MAX_CPUS 228 int "Maximum number of CPUs permitted for Layerscape" 229 default 4 if ARCH_LS1043A 230 default 4 if ARCH_LS1046A 231 default 16 if ARCH_LS2080A 232 default 1 233 help 234 Set this number to the maximum number of possible CPUs in the SoC. 235 SoCs may have multiple clusters with each cluster may have multiple 236 ports. If some ports are reserved but higher ports are used for 237 cores, count the reserved ports. This will allocate enough memory 238 in spin table to properly handle all cores. 239 240config SECURE_BOOT 241 bool "Secure Boot" 242 help 243 Enable Freescale Secure Boot feature 244 245config QSPI_AHB_INIT 246 bool "Init the QSPI AHB bus" 247 help 248 The default setting for QSPI AHB bus just support 3bytes addressing. 249 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 250 bus for those flashes to support the full QSPI flash size. 251 252config SYS_CCI400_OFFSET 253 hex "Offset for CCI400 base" 254 depends on SYS_FSL_HAS_CCI400 255 default 0x3090000 if ARCH_LS1088A 256 default 0x180000 if FSL_LSCH2 257 help 258 Offset for CCI400 base 259 CCI400 base addr = CCSRBAR + CCI400_OFFSET 260 261config SYS_FSL_IFC_BANK_COUNT 262 int "Maximum banks of Integrated flash controller" 263 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 264 default 4 if ARCH_LS1043A 265 default 4 if ARCH_LS1046A 266 default 8 if ARCH_LS2080A 267 268config SYS_FSL_HAS_CCI400 269 bool 270 271config SYS_FSL_HAS_DP_DDR 272 bool 273 274config SYS_FSL_SRDS_1 275 bool 276 277config SYS_FSL_SRDS_2 278 bool 279 280config SYS_HAS_SERDES 281 bool 282 283config FSL_TZASC_1 284 bool 285 286config FSL_TZASC_2 287 bool 288 289endmenu 290 291menu "Layerscape clock tree configuration" 292 depends on FSL_LSCH2 || FSL_LSCH3 293 294config SYS_FSL_CLK 295 bool "Enable clock tree initialization" 296 default y 297 298config CLUSTER_CLK_FREQ 299 int "Reference clock of core cluster" 300 depends on ARCH_LS1012A 301 default 100000000 302 help 303 This number is the reference clock frequency of core PLL. 304 For most platforms, the core PLL and Platform PLL have the same 305 reference clock, but for some platforms, LS1012A for instance, 306 they are provided sepatately. 307 308config SYS_FSL_PCLK_DIV 309 int "Platform clock divider" 310 default 1 if ARCH_LS1043A 311 default 1 if ARCH_LS1046A 312 default 2 313 help 314 This is the divider that is used to derive Platform clock from 315 Platform PLL, in another word: 316 Platform_clk = Platform_PLL_freq / this_divider 317 318config SYS_FSL_DSPI_CLK_DIV 319 int "DSPI clock divider" 320 default 1 if ARCH_LS1043A 321 default 2 322 help 323 This is the divider that is used to derive DSPI clock from Platform 324 clock, in another word DSPI_clk = Platform_clk / this_divider. 325 326config SYS_FSL_DUART_CLK_DIV 327 int "DUART clock divider" 328 default 1 if ARCH_LS1043A 329 default 2 330 help 331 This is the divider that is used to derive DUART clock from Platform 332 clock, in another word DUART_clk = Platform_clk / this_divider. 333 334config SYS_FSL_I2C_CLK_DIV 335 int "I2C clock divider" 336 default 1 if ARCH_LS1043A 337 default 2 338 help 339 This is the divider that is used to derive I2C clock from Platform 340 clock, in another word I2C_clk = Platform_clk / this_divider. 341 342config SYS_FSL_IFC_CLK_DIV 343 int "IFC clock divider" 344 default 1 if ARCH_LS1043A 345 default 2 346 help 347 This is the divider that is used to derive IFC clock from Platform 348 clock, in another word IFC_clk = Platform_clk / this_divider. 349 350config SYS_FSL_LPUART_CLK_DIV 351 int "LPUART clock divider" 352 default 1 if ARCH_LS1043A 353 default 2 354 help 355 This is the divider that is used to derive LPUART clock from Platform 356 clock, in another word LPUART_clk = Platform_clk / this_divider. 357 358config SYS_FSL_SDHC_CLK_DIV 359 int "SDHC clock divider" 360 default 1 if ARCH_LS1043A 361 default 1 if ARCH_LS1012A 362 default 2 363 help 364 This is the divider that is used to derive SDHC clock from Platform 365 clock, in another word SDHC_clk = Platform_clk / this_divider. 366endmenu 367 368config RESV_RAM 369 bool 370 help 371 Reserve memory from the top, tracked by gd->arch.resv_ram. This 372 reserved RAM can be used by special driver that resides in memory 373 after U-Boot exits. It's up to implementation to allocate and allow 374 access to this reserved memory. For example, the reserved RAM can 375 be at the high end of physical memory. The reserve RAM may be 376 excluded from memory bank(s) passed to OS, or marked as reserved. 377 378config SYS_FSL_ERRATUM_A008336 379 bool 380 381config SYS_FSL_ERRATUM_A008514 382 bool 383 384config SYS_FSL_ERRATUM_A008585 385 bool 386 387config SYS_FSL_ERRATUM_A008850 388 bool 389 390config SYS_FSL_ERRATUM_A009203 391 bool 392 393config SYS_FSL_ERRATUM_A009635 394 bool 395 396config SYS_FSL_ERRATUM_A009660 397 bool 398 399config SYS_FSL_ERRATUM_A009929 400 bool 401 402config SYS_MC_RSV_MEM_ALIGN 403 hex "Management Complex reserved memory alignment" 404 depends on RESV_RAM 405 default 0x20000000 406 help 407 Reserved memory needs to be aligned for MC to use. Default value 408 is 512MB. 409 410config SPL_LDSCRIPT 411 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 412