1config ARCH_LS1012A 2 bool 3 select ARMV8_SET_SMPEN 4 select FSL_LSCH2 5 select SYS_FSL_DDR_BE 6 select SYS_FSL_MMDC 7 select SYS_FSL_ERRATUM_A010315 8 9config ARCH_LS1043A 10 bool 11 select ARMV8_SET_SMPEN 12 select FSL_LSCH2 13 select SYS_FSL_DDR 14 select SYS_FSL_DDR_BE 15 select SYS_FSL_DDR_VER_50 16 select SYS_FSL_ERRATUM_A008850 17 select SYS_FSL_ERRATUM_A009660 18 select SYS_FSL_ERRATUM_A009663 19 select SYS_FSL_ERRATUM_A009929 20 select SYS_FSL_ERRATUM_A009942 21 select SYS_FSL_ERRATUM_A010315 22 select SYS_FSL_ERRATUM_A010539 23 select SYS_FSL_HAS_DDR3 24 select SYS_FSL_HAS_DDR4 25 26config ARCH_LS1046A 27 bool 28 select ARMV8_SET_SMPEN 29 select FSL_LSCH2 30 select SYS_FSL_DDR 31 select SYS_FSL_DDR_BE 32 select SYS_FSL_DDR_VER_50 33 select SYS_FSL_ERRATUM_A008511 34 select SYS_FSL_ERRATUM_A009801 35 select SYS_FSL_ERRATUM_A009803 36 select SYS_FSL_ERRATUM_A009942 37 select SYS_FSL_ERRATUM_A010165 38 select SYS_FSL_ERRATUM_A010539 39 select SYS_FSL_HAS_DDR4 40 select SYS_FSL_SRDS_2 41 42config ARCH_LS2080A 43 bool 44 select ARMV8_SET_SMPEN 45 select FSL_LSCH3 46 select SYS_FSL_DDR 47 select SYS_FSL_DDR_LE 48 select SYS_FSL_DDR_VER_50 49 select SYS_FSL_HAS_DP_DDR 50 select SYS_FSL_HAS_SEC 51 select SYS_FSL_HAS_DDR4 52 select SYS_FSL_SEC_COMPAT_5 53 select SYS_FSL_SEC_LE 54 select SYS_FSL_SRDS_2 55 select SYS_FSL_ERRATUM_A008336 56 select SYS_FSL_ERRATUM_A008511 57 select SYS_FSL_ERRATUM_A008514 58 select SYS_FSL_ERRATUM_A008585 59 select SYS_FSL_ERRATUM_A009635 60 select SYS_FSL_ERRATUM_A009663 61 select SYS_FSL_ERRATUM_A009801 62 select SYS_FSL_ERRATUM_A009803 63 select SYS_FSL_ERRATUM_A009942 64 select SYS_FSL_ERRATUM_A010165 65 66config FSL_LSCH2 67 bool 68 select SYS_FSL_HAS_SEC 69 select SYS_FSL_SEC_COMPAT_5 70 select SYS_FSL_SEC_BE 71 select SYS_FSL_SRDS_1 72 select SYS_HAS_SERDES 73 74config FSL_LSCH3 75 bool 76 select SYS_FSL_SRDS_1 77 select SYS_HAS_SERDES 78 79menu "Layerscape architecture" 80 depends on FSL_LSCH2 || FSL_LSCH3 81 82config FSL_PCIE_COMPAT 83 string "PCIe compatible of Kernel DT" 84 depends on PCIE_LAYERSCAPE 85 default "fsl,ls1012a-pcie" if ARCH_LS1012A 86 default "fsl,ls1043a-pcie" if ARCH_LS1043A 87 default "fsl,ls1046a-pcie" if ARCH_LS1046A 88 default "fsl,ls2080a-pcie" if ARCH_LS2080A 89 help 90 This compatible is used to find pci controller node in Kernel DT 91 to complete fixup. 92 93config HAS_FEATURE_GIC64K_ALIGN 94 bool 95 default y if ARCH_LS1043A 96 97config HAS_FEATURE_ENHANCED_MSI 98 bool 99 default y if ARCH_LS1043A 100 101menu "Layerscape PPA" 102config FSL_LS_PPA 103 bool "FSL Layerscape PPA firmware support" 104 depends on !ARMV8_PSCI 105 select ARMV8_SEC_FIRMWARE_SUPPORT 106 select SEC_FIRMWARE_ARMV8_PSCI 107 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 108 help 109 The FSL Primary Protected Application (PPA) is a software component 110 which is loaded during boot stage, and then remains resident in RAM 111 and runs in the TrustZone after boot. 112 Say y to enable it. 113choice 114 prompt "FSL Layerscape PPA firmware loading-media select" 115 depends on FSL_LS_PPA 116 default SYS_LS_PPA_FW_IN_XIP 117 118config SYS_LS_PPA_FW_IN_XIP 119 bool "XIP" 120 help 121 Say Y here if the PPA firmware locate at XIP flash, such 122 as NOR or QSPI flash. 123 124endchoice 125 126config SYS_LS_PPA_FW_ADDR 127 hex "Address of PPA firmware loading from" 128 depends on FSL_LS_PPA 129 default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT 130 default 0x60500000 if SYS_LS_PPA_FW_IN_XIP 131 help 132 If the PPA firmware locate at XIP flash, such as NOR or 133 QSPI flash, this address is a directly memory-mapped. 134 If it is in a serial accessed flash, such as NAND and SD 135 card, it is a byte offset. 136endmenu 137 138config SYS_FSL_ERRATUM_A010315 139 bool "Workaround for PCIe erratum A010315" 140 141config SYS_FSL_ERRATUM_A010539 142 bool "Workaround for PIN MUX erratum A010539" 143 144config MAX_CPUS 145 int "Maximum number of CPUs permitted for Layerscape" 146 default 4 if ARCH_LS1043A 147 default 4 if ARCH_LS1046A 148 default 16 if ARCH_LS2080A 149 default 1 150 help 151 Set this number to the maximum number of possible CPUs in the SoC. 152 SoCs may have multiple clusters with each cluster may have multiple 153 ports. If some ports are reserved but higher ports are used for 154 cores, count the reserved ports. This will allocate enough memory 155 in spin table to properly handle all cores. 156 157config SECURE_BOOT 158 bool "Secure Boot" 159 help 160 Enable Freescale Secure Boot feature 161 162config QSPI_AHB_INIT 163 bool "Init the QSPI AHB bus" 164 help 165 The default setting for QSPI AHB bus just support 3bytes addressing. 166 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 167 bus for those flashes to support the full QSPI flash size. 168 169config SYS_FSL_IFC_BANK_COUNT 170 int "Maximum banks of Integrated flash controller" 171 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 172 default 4 if ARCH_LS1043A 173 default 4 if ARCH_LS1046A 174 default 8 if ARCH_LS2080A 175 176config SYS_FSL_HAS_DP_DDR 177 bool 178 179config SYS_FSL_SRDS_1 180 bool 181 182config SYS_FSL_SRDS_2 183 bool 184 185config SYS_HAS_SERDES 186 bool 187 188endmenu 189 190menu "Layerscape clock tree configuration" 191 depends on FSL_LSCH2 || FSL_LSCH3 192 193config SYS_FSL_CLK 194 bool "Enable clock tree initialization" 195 default y 196 197config CLUSTER_CLK_FREQ 198 int "Reference clock of core cluster" 199 depends on ARCH_LS1012A 200 default 100000000 201 help 202 This number is the reference clock frequency of core PLL. 203 For most platforms, the core PLL and Platform PLL have the same 204 reference clock, but for some platforms, LS1012A for instance, 205 they are provided sepatately. 206 207config SYS_FSL_PCLK_DIV 208 int "Platform clock divider" 209 default 1 if ARCH_LS1043A 210 default 1 if ARCH_LS1046A 211 default 2 212 help 213 This is the divider that is used to derive Platform clock from 214 Platform PLL, in another word: 215 Platform_clk = Platform_PLL_freq / this_divider 216 217config SYS_FSL_DSPI_CLK_DIV 218 int "DSPI clock divider" 219 default 1 if ARCH_LS1043A 220 default 2 221 help 222 This is the divider that is used to derive DSPI clock from Platform 223 PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. 224 225config SYS_FSL_DUART_CLK_DIV 226 int "DUART clock divider" 227 default 1 if ARCH_LS1043A 228 default 2 229 help 230 This is the divider that is used to derive DUART clock from Platform 231 clock, in another word DUART_clk = Platform_clk / this_divider. 232 233config SYS_FSL_I2C_CLK_DIV 234 int "I2C clock divider" 235 default 1 if ARCH_LS1043A 236 default 2 237 help 238 This is the divider that is used to derive I2C clock from Platform 239 clock, in another word I2C_clk = Platform_clk / this_divider. 240 241config SYS_FSL_IFC_CLK_DIV 242 int "IFC clock divider" 243 default 1 if ARCH_LS1043A 244 default 2 245 help 246 This is the divider that is used to derive IFC clock from Platform 247 clock, in another word IFC_clk = Platform_clk / this_divider. 248 249config SYS_FSL_LPUART_CLK_DIV 250 int "LPUART clock divider" 251 default 1 if ARCH_LS1043A 252 default 2 253 help 254 This is the divider that is used to derive LPUART clock from Platform 255 clock, in another word LPUART_clk = Platform_clk / this_divider. 256 257config SYS_FSL_SDHC_CLK_DIV 258 int "SDHC clock divider" 259 default 1 if ARCH_LS1043A 260 default 1 if ARCH_LS1012A 261 default 2 262 help 263 This is the divider that is used to derive SDHC clock from Platform 264 clock, in another word SDHC_clk = Platform_clk / this_divider. 265endmenu 266 267config SYS_FSL_ERRATUM_A008336 268 bool 269 270config SYS_FSL_ERRATUM_A008514 271 bool 272 273config SYS_FSL_ERRATUM_A008585 274 bool 275 276config SYS_FSL_ERRATUM_A008850 277 bool 278 279config SYS_FSL_ERRATUM_A009635 280 bool 281 282config SYS_FSL_ERRATUM_A009660 283 bool 284 285config SYS_FSL_ERRATUM_A009929 286 bool 287