1/* 2 * (C) Copyright 2013 3 * David Feng <fenghua@phytium.com.cn> 4 * 5 * This file is based on sample code from ARMv8 ARM. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10#include <asm-offsets.h> 11#include <config.h> 12#include <asm/macro.h> 13#include <asm/system.h> 14#include <linux/linkage.h> 15 16/* 17 * void __asm_flush_dcache_level(level) 18 * 19 * clean and invalidate one level cache. 20 * 21 * x0: cache level 22 * x1: 0 flush & invalidate, 1 invalidate only 23 * x2~x9: clobbered 24 */ 25ENTRY(__asm_flush_dcache_level) 26 lsl x12, x0, #1 27 msr csselr_el1, x12 /* select cache level */ 28 isb /* sync change of cssidr_el1 */ 29 mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ 30 and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ 31 add x2, x2, #4 /* x2 <- log2(cache line size) */ 32 mov x3, #0x3ff 33 and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ 34 clz w5, w3 /* bit position of #ways */ 35 mov x4, #0x7fff 36 and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ 37 /* x12 <- cache level << 1 */ 38 /* x2 <- line length offset */ 39 /* x3 <- number of cache ways - 1 */ 40 /* x4 <- number of cache sets - 1 */ 41 /* x5 <- bit position of #ways */ 42 43loop_set: 44 mov x6, x3 /* x6 <- working copy of #ways */ 45loop_way: 46 lsl x7, x6, x5 47 orr x9, x12, x7 /* map way and level to cisw value */ 48 lsl x7, x4, x2 49 orr x9, x9, x7 /* map set number to cisw value */ 50 tbz w1, #0, 1f 51 dc isw, x9 52 b 2f 531: dc cisw, x9 /* clean & invalidate by set/way */ 542: subs x6, x6, #1 /* decrement the way */ 55 b.ge loop_way 56 subs x4, x4, #1 /* decrement the set */ 57 b.ge loop_set 58 59 ret 60ENDPROC(__asm_flush_dcache_level) 61 62/* 63 * void __asm_flush_dcache_all(int invalidate_only) 64 * 65 * x0: 0 flush & invalidate, 1 invalidate only 66 * 67 * clean and invalidate all data cache by SET/WAY. 68 */ 69ENTRY(__asm_dcache_all) 70 mov x1, x0 71 dsb sy 72 mrs x10, clidr_el1 /* read clidr_el1 */ 73 lsr x11, x10, #24 74 and x11, x11, #0x7 /* x11 <- loc */ 75 cbz x11, finished /* if loc is 0, exit */ 76 mov x15, lr 77 mov x0, #0 /* start flush at cache level 0 */ 78 /* x0 <- cache level */ 79 /* x10 <- clidr_el1 */ 80 /* x11 <- loc */ 81 /* x15 <- return address */ 82 83loop_level: 84 lsl x12, x0, #1 85 add x12, x12, x0 /* x0 <- tripled cache level */ 86 lsr x12, x10, x12 87 and x12, x12, #7 /* x12 <- cache type */ 88 cmp x12, #2 89 b.lt skip /* skip if no cache or icache */ 90 bl __asm_flush_dcache_level /* x1 = 0 flush, 1 invalidate */ 91skip: 92 add x0, x0, #1 /* increment cache level */ 93 cmp x11, x0 94 b.gt loop_level 95 96 mov x0, #0 97 msr csselr_el1, x0 /* restore csselr_el1 */ 98 dsb sy 99 isb 100 mov lr, x15 101 102finished: 103 ret 104ENDPROC(__asm_dcache_all) 105 106ENTRY(__asm_flush_dcache_all) 107 mov x16, lr 108 mov x0, #0 109 bl __asm_dcache_all 110 mov lr, x16 111 ret 112ENDPROC(__asm_flush_dcache_all) 113 114ENTRY(__asm_invalidate_dcache_all) 115 mov x16, lr 116 mov x0, #0x1 117 bl __asm_dcache_all 118 mov lr, x16 119 ret 120ENDPROC(__asm_invalidate_dcache_all) 121 122/* 123 * void __asm_flush_dcache_range(start, end) 124 * 125 * clean & invalidate data cache in the range 126 * 127 * x0: start address 128 * x1: end address 129 */ 130ENTRY(__asm_flush_dcache_range) 131 mrs x3, ctr_el0 132 lsr x3, x3, #16 133 and x3, x3, #0xf 134 mov x2, #4 135 lsl x2, x2, x3 /* cache line size */ 136 137 /* x2 <- minimal cache line size in cache system */ 138 sub x3, x2, #1 139 bic x0, x0, x3 1401: dc civac, x0 /* clean & invalidate data or unified cache */ 141 add x0, x0, x2 142 cmp x0, x1 143 b.lo 1b 144 dsb sy 145 ret 146ENDPROC(__asm_flush_dcache_range) 147 148/* 149 * void __asm_invalidate_icache_all(void) 150 * 151 * invalidate all tlb entries. 152 */ 153ENTRY(__asm_invalidate_icache_all) 154 ic ialluis 155 isb sy 156 ret 157ENDPROC(__asm_invalidate_icache_all) 158 159ENTRY(__asm_flush_l3_cache) 160 mov x0, #0 /* return status as success */ 161 ret 162ENDPROC(__asm_flush_l3_cache) 163 .weak __asm_flush_l3_cache 164 165/* 166 * void __asm_switch_ttbr(ulong new_ttbr) 167 * 168 * Safely switches to a new page table. 169 */ 170ENTRY(__asm_switch_ttbr) 171 /* x2 = SCTLR (alive throghout the function) */ 172 switch_el x4, 3f, 2f, 1f 1733: mrs x2, sctlr_el3 174 b 0f 1752: mrs x2, sctlr_el2 176 b 0f 1771: mrs x2, sctlr_el1 1780: 179 180 /* Unset CR_M | CR_C | CR_I from SCTLR to disable all caches */ 181 movn x1, #(CR_M | CR_C | CR_I) 182 and x1, x2, x1 183 switch_el x4, 3f, 2f, 1f 1843: msr sctlr_el3, x1 185 b 0f 1862: msr sctlr_el2, x1 187 b 0f 1881: msr sctlr_el1, x1 1890: isb 190 191 /* This call only clobbers x30 (lr) and x9 (unused) */ 192 mov x3, x30 193 bl __asm_invalidate_tlb_all 194 195 /* From here on we're running safely with caches disabled */ 196 197 /* Set TTBR to our first argument */ 198 switch_el x4, 3f, 2f, 1f 1993: msr ttbr0_el3, x0 200 b 0f 2012: msr ttbr0_el2, x0 202 b 0f 2031: msr ttbr0_el1, x0 2040: isb 205 206 /* Restore original SCTLR and thus enable caches again */ 207 switch_el x4, 3f, 2f, 1f 2083: msr sctlr_el3, x2 209 b 0f 2102: msr sctlr_el2, x2 211 b 0f 2121: msr sctlr_el1, x2 2130: isb 214 215 ret x3 216ENDPROC(__asm_switch_ttbr) 217