1if ARM64 2 3config ARMV8_MULTIENTRY 4 bool "Enable multiple CPUs to enter into U-Boot" 5 6config ARMV8_SET_SMPEN 7 bool "Enable data coherency with other cores in cluster" 8 help 9 Say Y here if there is not any trust firmware to set 10 CPUECTLR_EL1.SMPEN bit before U-Boot. 11 12 For A53, it enables data coherency with other cores in the 13 cluster, and for A57/A72, it enables receiving of instruction 14 cache and TLB maintenance operations. 15 Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even 16 for single core systems. Unfortunately write access to this 17 register may be controlled by EL3/EL2 firmware. To be more 18 precise, by default (if there is EL2/EL3 firmware running) 19 this register is RO for NS EL1. 20 This switch can be used to avoid writing to CPUECTLR_EL1, 21 it can be safely enabled when EL2/EL3 initialized SMPEN bit 22 or when CPU implementation doesn't include that register. 23 24config ARMV8_SPIN_TABLE 25 bool "Support spin-table enable method" 26 depends on ARMV8_MULTIENTRY && OF_LIBFDT 27 help 28 Say Y here to support "spin-table" enable method for booting Linux. 29 30 To use this feature, you must do: 31 - Specify enable-method = "spin-table" in each CPU node in the 32 Device Tree you are using to boot the kernel 33 - Let secondary CPUs in U-Boot (in a board specific manner) 34 before the master CPU jumps to the kernel 35 36 U-Boot automatically does: 37 - Set "cpu-release-addr" property of each CPU node 38 (overwrites it if already exists). 39 - Reserve the code for the spin-table and the release address 40 via a /memreserve/ region in the Device Tree. 41 42menu "ARMv8 secure monitor firmware" 43config ARMV8_SEC_FIRMWARE_SUPPORT 44 bool "Enable ARMv8 secure monitor firmware framework support" 45 select OF_LIBFDT 46 select FIT 47 help 48 This framework is aimed at making secure monitor firmware load 49 process brief. 50 Note: Only FIT format image is supported. 51 You should prepare and provide the below information: 52 - Address of secure firmware. 53 - Address to hold the return address from secure firmware. 54 - Secure firmware FIT image related information. 55 Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMEWARE_FIT_CNF_NAME 56 - The target exception level that secure monitor firmware will 57 return to. 58 59config SPL_ARMV8_SEC_FIRMWARE_SUPPORT 60 bool "Enable ARMv8 secure monitor firmware framework support for SPL" 61 select SPL_OF_LIBFDT 62 select SPL_FIT 63 help 64 Say Y here to support this framework in SPL phase. 65 66config SEC_FIRMWARE_ARMV8_PSCI 67 bool "PSCI implementation in secure monitor firmware" 68 depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT 69 help 70 This config enables the ARMv8 PSCI implementation in secure monitor 71 firmware. This is a private PSCI implementation and different from 72 those implemented under the common ARMv8 PSCI framework. 73 74config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT 75 bool "ARMv8 secure monitor firmware ERET address byteorder swap" 76 depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT 77 help 78 Say Y here when the endianness of the register or memory holding the 79 Secure firmware exception return address is different with core's. 80 81endmenu 82 83config PSCI_RESET 84 bool "Use PSCI for reset and shutdown" 85 default y 86 depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \ 87 !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \ 88 !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \ 89 !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \ 90 !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ 91 !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ 92 !ARCH_UNIPHIER && !ARCH_SNAPDRAGON && !TARGET_S32V234EVB 93 help 94 Most armv8 systems have PSCI support enabled in EL3, either through 95 ARM Trusted Firmware or other firmware. 96 97 On these systems, we do not need to implement system reset manually, 98 but can instead rely on higher level firmware to deal with it. 99 100 Select Y here to make use of PSCI calls for system reset 101 102config ARMV8_PSCI 103 bool "Enable PSCI support" if EXPERT 104 default n 105 help 106 PSCI is Power State Coordination Interface defined by ARM. 107 The PSCI in U-boot provides a general framework and each platform 108 can implement their own specific PSCI functions. 109 Say Y here to enable PSCI support on ARMv8 platform. 110 111config ARMV8_PSCI_NR_CPUS 112 int "Maximum supported CPUs for PSCI" 113 depends on ARMV8_PSCI 114 default 4 115 help 116 The maximum number of CPUs supported in the PSCI firmware. 117 It is no problem to set a larger value than the number of CPUs in 118 the actual hardware implementation. 119 120config ARMV8_PSCI_CPUS_PER_CLUSTER 121 int "Number of CPUs per cluster" 122 depends on ARMV8_PSCI 123 default 0 124 help 125 The number of CPUs per cluster, suppose each cluster has same number 126 of CPU cores, platforms with asymmetric clusters don't apply here. 127 A value 0 or no definition of it works for single cluster system. 128 System with multi-cluster should difine their own exact value. 129 130if SYS_HAS_ARMV8_SECURE_BASE 131 132config ARMV8_SECURE_BASE 133 hex "Secure address for PSCI image" 134 depends on ARMV8_PSCI 135 help 136 Address for placing the PSCI text, data and stack sections. 137 If not defined, the PSCI sections are placed together with the u-boot 138 but platform can choose to place PSCI code image separately in other 139 places such as some secure RAM built-in SOC etc. 140 141endif 142 143endif 144