1if ARM64 2 3config ARMV8_SPL_EXCEPTION_VECTORS 4 bool "Install crash dump exception vectors" 5 depends on SPL 6 default y 7 help 8 The default exception vector table is only used for the crash 9 dump, but still takes quite a lot of space in the image size. 10 11 Say N here if you are running out of code space in the image 12 and want to save some space at the cost of less debugging info. 13 14config ARMV8_MULTIENTRY 15 bool "Enable multiple CPUs to enter into U-Boot" 16 17config ARMV8_SET_SMPEN 18 bool "Enable data coherency with other cores in cluster" 19 help 20 Say Y here if there is not any trust firmware to set 21 CPUECTLR_EL1.SMPEN bit before U-Boot. 22 23 For A53, it enables data coherency with other cores in the 24 cluster, and for A57/A72, it enables receiving of instruction 25 cache and TLB maintenance operations. 26 Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even 27 for single core systems. Unfortunately write access to this 28 register may be controlled by EL3/EL2 firmware. To be more 29 precise, by default (if there is EL2/EL3 firmware running) 30 this register is RO for NS EL1. 31 This switch can be used to avoid writing to CPUECTLR_EL1, 32 it can be safely enabled when EL2/EL3 initialized SMPEN bit 33 or when CPU implementation doesn't include that register. 34 35config ARMV8_SPIN_TABLE 36 bool "Support spin-table enable method" 37 depends on ARMV8_MULTIENTRY && OF_LIBFDT 38 help 39 Say Y here to support "spin-table" enable method for booting Linux. 40 41 To use this feature, you must do: 42 - Specify enable-method = "spin-table" in each CPU node in the 43 Device Tree you are using to boot the kernel 44 - Bring secondary CPUs into U-Boot proper in a board specific 45 manner. This must be done *after* relocation. Otherwise, the 46 secondary CPUs will spin in unprotected memory area because the 47 master CPU protects the relocated spin code. 48 49 U-Boot automatically does: 50 - Set "cpu-release-addr" property of each CPU node 51 (overwrites it if already exists). 52 - Reserve the code for the spin-table and the release address 53 via a /memreserve/ region in the Device Tree. 54 55menu "ARMv8 secure monitor firmware" 56config ARMV8_SEC_FIRMWARE_SUPPORT 57 bool "Enable ARMv8 secure monitor firmware framework support" 58 select FIT 59 select OF_LIBFDT 60 help 61 This framework is aimed at making secure monitor firmware load 62 process brief. 63 Note: Only FIT format image is supported. 64 You should prepare and provide the below information: 65 - Address of secure firmware. 66 - Address to hold the return address from secure firmware. 67 - Secure firmware FIT image related information. 68 Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMEWARE_FIT_CNF_NAME 69 - The target exception level that secure monitor firmware will 70 return to. 71 72config SPL_ARMV8_SEC_FIRMWARE_SUPPORT 73 bool "Enable ARMv8 secure monitor firmware framework support for SPL" 74 select SPL_FIT 75 select SPL_OF_LIBFDT 76 help 77 Say Y here to support this framework in SPL phase. 78 79config SEC_FIRMWARE_ARMV8_PSCI 80 bool "PSCI implementation in secure monitor firmware" 81 depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT 82 help 83 This config enables the ARMv8 PSCI implementation in secure monitor 84 firmware. This is a private PSCI implementation and different from 85 those implemented under the common ARMv8 PSCI framework. 86 87config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT 88 bool "ARMv8 secure monitor firmware ERET address byteorder swap" 89 depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT 90 help 91 Say Y here when the endianness of the register or memory holding the 92 Secure firmware exception return address is different with core's. 93 94endmenu 95 96config PSCI_RESET 97 bool "Use PSCI for reset and shutdown" 98 default y 99 depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \ 100 !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \ 101 !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \ 102 !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \ 103 !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \ 104 !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \ 105 !TARGET_LS1012AFRWY && \ 106 !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ 107 !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ 108 !TARGET_LS2081ARDB && \ 109 !ARCH_UNIPHIER && !TARGET_S32V234EVB 110 help 111 Most armv8 systems have PSCI support enabled in EL3, either through 112 ARM Trusted Firmware or other firmware. 113 114 On these systems, we do not need to implement system reset manually, 115 but can instead rely on higher level firmware to deal with it. 116 117 Select Y here to make use of PSCI calls for system reset 118 119config ARMV8_PSCI 120 bool "Enable PSCI support" if EXPERT 121 default n 122 help 123 PSCI is Power State Coordination Interface defined by ARM. 124 The PSCI in U-boot provides a general framework and each platform 125 can implement their own specific PSCI functions. 126 Say Y here to enable PSCI support on ARMv8 platform. 127 128config ARMV8_PSCI_NR_CPUS 129 int "Maximum supported CPUs for PSCI" 130 depends on ARMV8_PSCI 131 default 4 132 help 133 The maximum number of CPUs supported in the PSCI firmware. 134 It is no problem to set a larger value than the number of CPUs in 135 the actual hardware implementation. 136 137config ARMV8_PSCI_CPUS_PER_CLUSTER 138 int "Number of CPUs per cluster" 139 depends on ARMV8_PSCI 140 default 0 141 help 142 The number of CPUs per cluster, suppose each cluster has same number 143 of CPU cores, platforms with asymmetric clusters don't apply here. 144 A value 0 or no definition of it works for single cluster system. 145 System with multi-cluster should difine their own exact value. 146 147config ARMV8_EA_EL3_FIRST 148 bool "External aborts and SError interrupt exception are taken in EL3" 149 default n 150 help 151 Exception handling at all exception levels for External Abort and 152 SError interrupt exception are taken in EL3. 153 154if SYS_HAS_ARMV8_SECURE_BASE 155 156config ARMV8_SECURE_BASE 157 hex "Secure address for PSCI image" 158 depends on ARMV8_PSCI 159 help 160 Address for placing the PSCI text, data and stack sections. 161 If not defined, the PSCI sections are placed together with the u-boot 162 but platform can choose to place PSCI code image separately in other 163 places such as some secure RAM built-in SOC etc. 164 165endif 166 167endif 168