1if ARM64 2 3config ARMV8_MULTIENTRY 4 bool "Enable multiple CPUs to enter into U-Boot" 5 6config ARMV8_SET_SMPEN 7 bool "Enable data coherency with other cores in cluster" 8 help 9 Say Y here if there is not any trust firmware to set 10 CPUECTLR_EL1.SMPEN bit before U-Boot. 11 12 For A53, it enables data coherency with other cores in the 13 cluster, and for A57/A72, it enables receiving of instruction 14 cache and TLB maintenance operations. 15 Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even 16 for single core systems. Unfortunately write access to this 17 register may be controlled by EL3/EL2 firmware. To be more 18 precise, by default (if there is EL2/EL3 firmware running) 19 this register is RO for NS EL1. 20 This switch can be used to avoid writing to CPUECTLR_EL1, 21 it can be safely enabled when EL2/EL3 initialized SMPEN bit 22 or when CPU implementation doesn't include that register. 23 24config ARMV8_SPIN_TABLE 25 bool "Support spin-table enable method" 26 depends on ARMV8_MULTIENTRY && OF_LIBFDT 27 help 28 Say Y here to support "spin-table" enable method for booting Linux. 29 30 To use this feature, you must do: 31 - Specify enable-method = "spin-table" in each CPU node in the 32 Device Tree you are using to boot the kernel 33 - Let secondary CPUs in U-Boot (in a board specific manner) 34 before the master CPU jumps to the kernel 35 36 U-Boot automatically does: 37 - Set "cpu-release-addr" property of each CPU node 38 (overwrites it if already exists). 39 - Reserve the code for the spin-table and the release address 40 via a /memreserve/ region in the Device Tree. 41 42config PSCI_RESET 43 bool "Use PSCI for reset and shutdown" 44 default y 45 depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \ 46 !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \ 47 !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \ 48 !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \ 49 !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \ 50 !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ 51 !ARCH_UNIPHIER && !ARCH_SNAPDRAGON && !TARGET_S32V234EVB 52 help 53 Most armv8 systems have PSCI support enabled in EL3, either through 54 ARM Trusted Firmware or other firmware. 55 56 On these systems, we do not need to implement system reset manually, 57 but can instead rely on higher level firmware to deal with it. 58 59 Select Y here to make use of PSCI calls for system reset 60 61config ARMV8_PSCI 62 bool "Enable PSCI support" if EXPERT 63 default n 64 help 65 PSCI is Power State Coordination Interface defined by ARM. 66 The PSCI in U-boot provides a general framework and each platform 67 can implement their own specific PSCI functions. 68 Say Y here to enable PSCI support on ARMv8 platform. 69 70config ARMV8_PSCI_NR_CPUS 71 int "Maximum supported CPUs for PSCI" 72 depends on ARMV8_PSCI 73 default 4 74 help 75 The maximum number of CPUs supported in the PSCI firmware. 76 It is no problem to set a larger value than the number of CPUs in 77 the actual hardware implementation. 78 79config ARMV8_PSCI_CPUS_PER_CLUSTER 80 int "Number of CPUs per cluster" 81 depends on ARMV8_PSCI 82 default 0 83 help 84 The number of CPUs per cluster, suppose each cluster has same number 85 of CPU cores, platforms with asymmetric clusters don't apply here. 86 A value 0 or no definition of it works for single cluster system. 87 System with multi-cluster should difine their own exact value. 88 89if SYS_HAS_ARMV8_SECURE_BASE 90 91config ARMV8_SECURE_BASE 92 hex "Secure address for PSCI image" 93 depends on ARMV8_PSCI 94 help 95 Address for placing the PSCI text, data and stack sections. 96 If not defined, the PSCI sections are placed together with the u-boot 97 but platform can choose to place PSCI code image separately in other 98 places such as some secure RAM built-in SOC etc. 99 100endif 101 102endif 103