xref: /openbmc/u-boot/arch/arm/cpu/armv8/Kconfig (revision 41826f6a)
1if ARM64
2
3config ARMV8_MULTIENTRY
4        bool "Enable multiple CPUs to enter into U-Boot"
5
6config ARMV8_SET_SMPEN
7        bool "Enable data coherency with other cores in cluster"
8        help
9	  Say Y here if there is not any trust firmware to set
10	  CPUECTLR_EL1.SMPEN bit before U-Boot.
11
12	  For A53, it enables data coherency with other cores in the
13	  cluster, and for A57/A72, it enables receiving of instruction
14	  cache and TLB maintenance operations.
15	  Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even
16	  for single core systems. Unfortunately write access to this
17	  register may be controlled by EL3/EL2 firmware. To be more
18	  precise, by default (if there is EL2/EL3 firmware running)
19	  this register is RO for NS EL1.
20	  This switch can be used to avoid writing to CPUECTLR_EL1,
21	  it can be safely enabled when EL2/EL3 initialized SMPEN bit
22	  or when CPU implementation doesn't include that register.
23
24config ARMV8_SPIN_TABLE
25	bool "Support spin-table enable method"
26	depends on ARMV8_MULTIENTRY && OF_LIBFDT
27	help
28	  Say Y here to support "spin-table" enable method for booting Linux.
29
30	  To use this feature, you must do:
31	    - Specify enable-method = "spin-table" in each CPU node in the
32	      Device Tree you are using to boot the kernel
33	    - Bring secondary CPUs into U-Boot proper in a board specific
34	      manner.  This must be done *after* relocation.  Otherwise, the
35	      secondary CPUs will spin in unprotected memory area because the
36	      master CPU protects the relocated spin code.
37
38	  U-Boot automatically does:
39	    - Set "cpu-release-addr" property of each CPU node
40	      (overwrites it if already exists).
41	    - Reserve the code for the spin-table and the release address
42	      via a /memreserve/ region in the Device Tree.
43
44menu "ARMv8 secure monitor firmware"
45config ARMV8_SEC_FIRMWARE_SUPPORT
46	bool "Enable ARMv8 secure monitor firmware framework support"
47	select OF_LIBFDT
48	select FIT
49	help
50	  This framework is aimed at making secure monitor firmware load
51	  process brief.
52	  Note: Only FIT format image is supported.
53	  You should prepare and provide the below information:
54	    - Address of secure firmware.
55	    - Address to hold the return address from secure firmware.
56	    - Secure firmware FIT image related information.
57	      Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMEWARE_FIT_CNF_NAME
58	    - The target exception level that secure monitor firmware will
59	      return to.
60
61config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
62	bool "Enable ARMv8 secure monitor firmware framework support for SPL"
63	select SPL_OF_LIBFDT
64	select SPL_FIT
65	help
66	  Say Y here to support this framework in SPL phase.
67
68config SEC_FIRMWARE_ARMV8_PSCI
69	bool "PSCI implementation in secure monitor firmware"
70	depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
71	help
72	  This config enables the ARMv8 PSCI implementation in secure monitor
73	  firmware. This is a private PSCI implementation and different from
74	  those implemented under the common ARMv8 PSCI framework.
75
76config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
77	bool "ARMv8 secure monitor firmware ERET address byteorder swap"
78	depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
79	help
80	  Say Y here when the endianness of the register or memory holding the
81	  Secure firmware exception return address is different with core's.
82
83endmenu
84
85config PSCI_RESET
86	bool "Use PSCI for reset and shutdown"
87	default y
88	depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \
89		   !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
90		   !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
91		   !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
92		   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
93		   !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
94		   !TARGET_LS1012AFRWY && \
95		   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
96		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
97		   !TARGET_LS2081ARDB && \
98		   !ARCH_UNIPHIER && !TARGET_S32V234EVB
99	help
100	  Most armv8 systems have PSCI support enabled in EL3, either through
101	  ARM Trusted Firmware or other firmware.
102
103	  On these systems, we do not need to implement system reset manually,
104	  but can instead rely on higher level firmware to deal with it.
105
106	  Select Y here to make use of PSCI calls for system reset
107
108config ARMV8_PSCI
109	bool "Enable PSCI support" if EXPERT
110	default n
111	help
112	  PSCI is Power State Coordination Interface defined by ARM.
113	  The PSCI in U-boot provides a general framework and each platform
114	  can implement their own specific PSCI functions.
115	  Say Y here to enable PSCI support on ARMv8 platform.
116
117config ARMV8_PSCI_NR_CPUS
118	int "Maximum supported CPUs for PSCI"
119	depends on ARMV8_PSCI
120	default 4
121	help
122	  The maximum number of CPUs supported in the PSCI firmware.
123	  It is no problem to set a larger value than the number of CPUs in
124	  the actual hardware implementation.
125
126config ARMV8_PSCI_CPUS_PER_CLUSTER
127	int "Number of CPUs per cluster"
128	depends on ARMV8_PSCI
129	default 0
130	help
131	  The number of CPUs per cluster, suppose each cluster has same number
132	  of CPU cores, platforms with asymmetric clusters don't apply here.
133	  A value 0 or no definition of it works for single cluster system.
134	  System with multi-cluster should difine their own exact value.
135
136if SYS_HAS_ARMV8_SECURE_BASE
137
138config ARMV8_SECURE_BASE
139	hex "Secure address for PSCI image"
140	depends on ARMV8_PSCI
141	help
142	  Address for placing the PSCI text, data and stack sections.
143	  If not defined, the PSCI sections are placed together with the u-boot
144	  but platform can choose to place PSCI code image separately in other
145	  places such as some secure RAM built-in SOC etc.
146
147endif
148
149endif
150