xref: /openbmc/u-boot/arch/arm/cpu/armv8/Kconfig (revision 14bf25d5)
123b5877cSLinus Walleijif ARM64
223b5877cSLinus Walleij
323b5877cSLinus Walleijconfig ARMV8_MULTIENTRY
4ab65006bSMasahiro Yamada        bool "Enable multiple CPUs to enter into U-Boot"
523b5877cSLinus Walleij
66b6024eaSMasahiro Yamadaconfig ARMV8_SPIN_TABLE
76b6024eaSMasahiro Yamada	bool "Support spin-table enable method"
86b6024eaSMasahiro Yamada	depends on ARMV8_MULTIENTRY && OF_LIBFDT
96b6024eaSMasahiro Yamada	help
106b6024eaSMasahiro Yamada	  Say Y here to support "spin-table" enable method for booting Linux.
116b6024eaSMasahiro Yamada
126b6024eaSMasahiro Yamada	  To use this feature, you must do:
136b6024eaSMasahiro Yamada	    - Specify enable-method = "spin-table" in each CPU node in the
146b6024eaSMasahiro Yamada	      Device Tree you are using to boot the kernel
156b6024eaSMasahiro Yamada	    - Let secondary CPUs in U-Boot (in a board specific manner)
166b6024eaSMasahiro Yamada	      before the master CPU jumps to the kernel
176b6024eaSMasahiro Yamada
186b6024eaSMasahiro Yamada	  U-Boot automatically does:
196b6024eaSMasahiro Yamada	    - Set "cpu-release-addr" property of each CPU node
206b6024eaSMasahiro Yamada	      (overwrites it if already exists).
216b6024eaSMasahiro Yamada	    - Reserve the code for the spin-table and the release address
226b6024eaSMasahiro Yamada	      via a /memreserve/ region in the Device Tree.
236b6024eaSMasahiro Yamada
248069821fSAlexander Grafconfig PSCI_RESET
258069821fSAlexander Graf	bool "Use PSCI for reset and shutdown"
268069821fSAlexander Graf	default y
278069821fSAlexander Graf	depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
288069821fSAlexander Graf		   !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
298069821fSAlexander Graf		   !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
308069821fSAlexander Graf		   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
31441a2306SAlexander Graf		   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
32441a2306SAlexander Graf		   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
33441a2306SAlexander Graf		   !ARCH_UNIPHIER && !ARCH_SNAPDRAGON && !TARGET_S32V234EVB
348069821fSAlexander Graf	help
358069821fSAlexander Graf	  Most armv8 systems have PSCI support enabled in EL3, either through
368069821fSAlexander Graf	  ARM Trusted Firmware or other firmware.
378069821fSAlexander Graf
388069821fSAlexander Graf	  On these systems, we do not need to implement system reset manually,
398069821fSAlexander Graf	  but can instead rely on higher level firmware to deal with it.
408069821fSAlexander Graf
418069821fSAlexander Graf	  Select Y here to make use of PSCI calls for system reset
428069821fSAlexander Graf
43df88cb3bSmacro.wave.z@gmail.comconfig ARMV8_PSCI
44df88cb3bSmacro.wave.z@gmail.com	bool "Enable PSCI support" if EXPERT
45df88cb3bSmacro.wave.z@gmail.com	default n
46df88cb3bSmacro.wave.z@gmail.com	help
47df88cb3bSmacro.wave.z@gmail.com	  PSCI is Power State Coordination Interface defined by ARM.
48df88cb3bSmacro.wave.z@gmail.com	  The PSCI in U-boot provides a general framework and each platform
49df88cb3bSmacro.wave.z@gmail.com	  can implement their own specific PSCI functions.
50df88cb3bSmacro.wave.z@gmail.com	  Say Y here to enable PSCI support on ARMv8 platform.
51df88cb3bSmacro.wave.z@gmail.com
52df88cb3bSmacro.wave.z@gmail.comconfig ARMV8_PSCI_NR_CPUS
53df88cb3bSmacro.wave.z@gmail.com	int "Maximum supported CPUs for PSCI"
54df88cb3bSmacro.wave.z@gmail.com	depends on ARMV8_PSCI
55df88cb3bSmacro.wave.z@gmail.com	default 4
56df88cb3bSmacro.wave.z@gmail.com	help
57df88cb3bSmacro.wave.z@gmail.com	  The maximum number of CPUs supported in the PSCI firmware.
58df88cb3bSmacro.wave.z@gmail.com	  It is no problem to set a larger value than the number of CPUs in
59df88cb3bSmacro.wave.z@gmail.com	  the actual hardware implementation.
60df88cb3bSmacro.wave.z@gmail.com
61*14bf25d5Smacro.wave.z@gmail.comconfig ARMV8_PSCI_CPUS_PER_CLUSTER
62*14bf25d5Smacro.wave.z@gmail.com	int "Number of CPUs per cluster"
63*14bf25d5Smacro.wave.z@gmail.com	depends on ARMV8_PSCI
64*14bf25d5Smacro.wave.z@gmail.com	default 0
65*14bf25d5Smacro.wave.z@gmail.com	help
66*14bf25d5Smacro.wave.z@gmail.com	  The number of CPUs per cluster, suppose each cluster has same number
67*14bf25d5Smacro.wave.z@gmail.com	  of CPU cores, platforms with asymmetric clusters don't apply here.
68*14bf25d5Smacro.wave.z@gmail.com	  A value 0 or no definition of it works for single cluster system.
69*14bf25d5Smacro.wave.z@gmail.com	  System with multi-cluster should difine their own exact value.
70*14bf25d5Smacro.wave.z@gmail.com
71df88cb3bSmacro.wave.z@gmail.comif SYS_HAS_ARMV8_SECURE_BASE
72df88cb3bSmacro.wave.z@gmail.com
73df88cb3bSmacro.wave.z@gmail.comconfig ARMV8_SECURE_BASE
74df88cb3bSmacro.wave.z@gmail.com	hex "Secure address for PSCI image"
75df88cb3bSmacro.wave.z@gmail.com	depends on ARMV8_PSCI
76df88cb3bSmacro.wave.z@gmail.com	help
77df88cb3bSmacro.wave.z@gmail.com	  Address for placing the PSCI text, data and stack sections.
78df88cb3bSmacro.wave.z@gmail.com	  If not defined, the PSCI sections are placed together with the u-boot
79df88cb3bSmacro.wave.z@gmail.com	  but platform can choose to place PSCI code image separately in other
80df88cb3bSmacro.wave.z@gmail.com	  places such as some secure RAM built-in SOC etc.
81df88cb3bSmacro.wave.z@gmail.com
82df88cb3bSmacro.wave.z@gmail.comendif
83df88cb3bSmacro.wave.z@gmail.com
8423b5877cSLinus Walleijendif
85