1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * ARM Cortex M3/M4/M7 SysTick timer driver 4 * (C) Copyright 2017 Renesas Electronics Europe Ltd 5 * 6 * Based on arch/arm/mach-stm32/stm32f1/timer.c 7 * (C) Copyright 2015 8 * Kamil Lulko, <kamil.lulko@gmail.com> 9 * 10 * Copyright 2015 ATS Advanced Telematics Systems GmbH 11 * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> 12 * 13 * The SysTick timer is a 24-bit count down timer. The clock can be either the 14 * CPU clock or a reference clock. Since the timer will wrap around very quickly 15 * when using the CPU clock, and we do not handle the timer interrupts, it is 16 * expected that this driver is only ever used with a slow reference clock. 17 * 18 * The number of reference clock ticks that correspond to 10ms is normally 19 * defined in the SysTick Calibration register's TENMS field. However, on some 20 * devices this is wrong, so this driver allows the clock rate to be defined 21 * using CONFIG_SYS_HZ_CLOCK. 22 */ 23 24 #include <common.h> 25 #include <asm/io.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 /* SysTick Base Address - fixed for all Cortex M3, M4 and M7 devices */ 30 #define SYSTICK_BASE 0xE000E010 31 32 struct cm3_systick { 33 uint32_t ctrl; 34 uint32_t reload_val; 35 uint32_t current_val; 36 uint32_t calibration; 37 }; 38 39 #define TIMER_MAX_VAL 0x00FFFFFF 40 #define SYSTICK_CTRL_EN BIT(0) 41 /* Clock source: 0 = Ref clock, 1 = CPU clock */ 42 #define SYSTICK_CTRL_CPU_CLK BIT(2) 43 #define SYSTICK_CAL_NOREF BIT(31) 44 #define SYSTICK_CAL_SKEW BIT(30) 45 #define SYSTICK_CAL_TENMS_MASK 0x00FFFFFF 46 47 /* read the 24-bit timer */ 48 static ulong read_timer(void) 49 { 50 struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE; 51 52 /* The timer counts down, therefore convert to an incrementing timer */ 53 return TIMER_MAX_VAL - readl(&systick->current_val); 54 } 55 56 int timer_init(void) 57 { 58 struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE; 59 u32 cal; 60 61 writel(TIMER_MAX_VAL, &systick->reload_val); 62 /* Any write to current_val reg clears it to 0 */ 63 writel(0, &systick->current_val); 64 65 cal = readl(&systick->calibration); 66 if (cal & SYSTICK_CAL_NOREF) 67 /* Use CPU clock, no interrupts */ 68 writel(SYSTICK_CTRL_EN | SYSTICK_CTRL_CPU_CLK, &systick->ctrl); 69 else 70 /* Use external clock, no interrupts */ 71 writel(SYSTICK_CTRL_EN, &systick->ctrl); 72 73 /* 74 * If the TENMS field is inexact or wrong, specify the clock rate using 75 * CONFIG_SYS_HZ_CLOCK. 76 */ 77 #if defined(CONFIG_SYS_HZ_CLOCK) 78 gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK; 79 #else 80 gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100; 81 #endif 82 83 gd->arch.tbl = 0; 84 gd->arch.tbu = 0; 85 gd->arch.lastinc = read_timer(); 86 87 return 0; 88 } 89 90 /* return milli-seconds timer value */ 91 ulong get_timer(ulong base) 92 { 93 unsigned long long t = get_ticks() * 1000; 94 95 return (ulong)((t / gd->arch.timer_rate_hz)) - base; 96 } 97 98 unsigned long long get_ticks(void) 99 { 100 u32 now = read_timer(); 101 102 if (now >= gd->arch.lastinc) 103 gd->arch.tbl += (now - gd->arch.lastinc); 104 else 105 gd->arch.tbl += (TIMER_MAX_VAL - gd->arch.lastinc) + now; 106 107 gd->arch.lastinc = now; 108 109 return gd->arch.tbl; 110 } 111 112 ulong get_tbclk(void) 113 { 114 return gd->arch.timer_rate_hz; 115 } 116