1 /* 2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <linux/bitops.h> 9 #include <asm/armv7m.h> 10 #include <asm/armv7m_mpu.h> 11 #include <asm/io.h> 12 13 #define V7M_MPU_CTRL_ENABLE BIT(0) 14 #define V7M_MPU_CTRL_DISABLE (0 << 0) 15 #define V7M_MPU_CTRL_HFNMIENA BIT(1) 16 #define V7M_MPU_CTRL_PRIVDEFENA BIT(2) 17 #define VALID_REGION BIT(4) 18 19 #define ENABLE_REGION BIT(0) 20 21 #define AP_SHIFT 24 22 #define XN_SHIFT 28 23 #define TEX_SHIFT 19 24 #define S_SHIFT 18 25 #define C_SHIFT 17 26 #define B_SHIFT 16 27 #define REGION_SIZE_SHIFT 1 28 29 #define CACHEABLE (1 << C_SHIFT) 30 #define BUFFERABLE (1 << B_SHIFT) 31 #define SHAREABLE (1 << S_SHIFT) 32 33 void disable_mpu(void) 34 { 35 writel(0, &V7M_MPU->ctrl); 36 } 37 38 void enable_mpu(void) 39 { 40 writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_PRIVDEFENA, &V7M_MPU->ctrl); 41 42 /* Make sure new mpu config is effective for next memory access */ 43 dsb(); 44 isb(); /* Make sure instruction stream sees it */ 45 } 46 47 void mpu_config(struct mpu_region_config *reg_config) 48 { 49 uint32_t attr; 50 51 switch (reg_config->mr_attr) { 52 case STRONG_ORDER: 53 attr = SHAREABLE; 54 break; 55 case SHARED_WRITE_BUFFERED: 56 attr = BUFFERABLE; 57 break; 58 case O_I_WT_NO_WR_ALLOC: 59 attr = CACHEABLE; 60 break; 61 case O_I_WB_NO_WR_ALLOC: 62 attr = CACHEABLE | BUFFERABLE; 63 break; 64 case O_I_NON_CACHEABLE: 65 attr = 1 << TEX_SHIFT; 66 break; 67 case O_I_WB_RD_WR_ALLOC: 68 attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE; 69 break; 70 case DEVICE_NON_SHARED: 71 attr = (2 << TEX_SHIFT) | BUFFERABLE; 72 break; 73 default: 74 attr = 0; /* strongly ordered */ 75 break; 76 }; 77 78 writel(reg_config->start_addr | VALID_REGION | reg_config->region_no, 79 &V7M_MPU->rbar); 80 81 writel(reg_config->xn << XN_SHIFT | reg_config->ap << AP_SHIFT | attr 82 | reg_config->reg_size << REGION_SIZE_SHIFT | ENABLE_REGION 83 , &V7M_MPU->rasr); 84 } 85