1 /* 2 * (C) Copyright 2013 3 * Andre Przywara, Linaro 4 * 5 * Routines to transition ARMv7 processors from secure into non-secure state 6 * and from non-secure SVC into HYP mode 7 * needed to enable ARMv7 virtualization for current hypervisors 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28 #include <common.h> 29 #include <asm/armv7.h> 30 #include <asm/gic.h> 31 #include <asm/io.h> 32 33 unsigned long gic_dist_addr; 34 35 static unsigned int read_cpsr(void) 36 { 37 unsigned int reg; 38 39 asm volatile ("mrs %0, cpsr\n" : "=r" (reg)); 40 return reg; 41 } 42 43 static unsigned int read_id_pfr1(void) 44 { 45 unsigned int reg; 46 47 asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg)); 48 return reg; 49 } 50 51 static unsigned long get_gicd_base_address(void) 52 { 53 #ifdef CONFIG_ARM_GIC_BASE_ADDRESS 54 return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; 55 #else 56 unsigned midr; 57 unsigned periphbase; 58 59 /* check whether we are an Cortex-A15 or A7. 60 * The actual HYP switch should work with all CPUs supporting 61 * the virtualization extension, but we need the GIC address, 62 * which we know only for sure for those two CPUs. 63 */ 64 asm("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr)); 65 switch (midr & MIDR_PRIMARY_PART_MASK) { 66 case MIDR_CORTEX_A9_R0P1: 67 case MIDR_CORTEX_A15_R0P0: 68 case MIDR_CORTEX_A7_R0P0: 69 break; 70 default: 71 printf("nonsec: could not determine GIC address.\n"); 72 return -1; 73 } 74 75 /* get the GIC base address from the CBAR register */ 76 asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase)); 77 78 /* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to 79 * encode this). Bail out here since we cannot access this without 80 * enabling paging. 81 */ 82 if ((periphbase & 0xff) != 0) { 83 printf("nonsec: PERIPHBASE is above 4 GB, no access.\n"); 84 return -1; 85 } 86 87 return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET; 88 #endif 89 } 90 91 static void kick_secondary_cpus_gic(unsigned long gicdaddr) 92 { 93 /* kick all CPUs (except this one) by writing to GICD_SGIR */ 94 writel(1U << 24, gicdaddr + GICD_SGIR); 95 } 96 97 void __weak smp_kick_all_cpus(void) 98 { 99 kick_secondary_cpus_gic(gic_dist_addr); 100 } 101 102 int armv7_switch_hyp(void) 103 { 104 unsigned int reg; 105 106 /* check whether we are in HYP mode already */ 107 if ((read_cpsr() & 0x1f) == 0x1a) { 108 debug("CPU already in HYP mode\n"); 109 return 0; 110 } 111 112 /* check whether the CPU supports the virtualization extensions */ 113 reg = read_id_pfr1(); 114 if ((reg & CPUID_ARM_VIRT_MASK) != 1 << CPUID_ARM_VIRT_SHIFT) { 115 printf("HYP mode: Virtualization extensions not implemented.\n"); 116 return -1; 117 } 118 119 /* call the HYP switching code on this CPU also */ 120 _switch_to_hyp(); 121 122 if ((read_cpsr() & 0x1F) != 0x1a) { 123 printf("HYP mode: switch not successful.\n"); 124 return -1; 125 } 126 127 return 0; 128 } 129 130 int armv7_switch_nonsec(void) 131 { 132 unsigned int reg; 133 unsigned itlinesnr, i; 134 135 /* check whether the CPU supports the security extensions */ 136 reg = read_id_pfr1(); 137 if ((reg & 0xF0) == 0) { 138 printf("nonsec: Security extensions not implemented.\n"); 139 return -1; 140 } 141 142 /* the SCR register will be set directly in the monitor mode handler, 143 * according to the spec one should not tinker with it in secure state 144 * in SVC mode. Do not try to read it once in non-secure state, 145 * any access to it will trap. 146 */ 147 148 gic_dist_addr = get_gicd_base_address(); 149 if (gic_dist_addr == -1) 150 return -1; 151 152 /* enable the GIC distributor */ 153 writel(readl(gic_dist_addr + GICD_CTLR) | 0x03, 154 gic_dist_addr + GICD_CTLR); 155 156 /* TYPER[4:0] contains an encoded number of available interrupts */ 157 itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f; 158 159 /* set all bits in the GIC group registers to one to allow access 160 * from non-secure state. The first 32 interrupts are private per 161 * CPU and will be set later when enabling the GIC for each core 162 */ 163 for (i = 1; i <= itlinesnr; i++) 164 writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i); 165 166 smp_set_core_boot_addr((unsigned long)_smp_pen, -1); 167 smp_kick_all_cpus(); 168 169 /* call the non-sec switching code on this CPU also */ 170 _nonsec_init(); 171 172 return 0; 173 } 174