1 /* 2 * (C) Copyright 2013 3 * Andre Przywara, Linaro <andre.przywara@linaro.org> 4 * 5 * Routines to transition ARMv7 processors from secure into non-secure state 6 * and from non-secure SVC into HYP mode 7 * needed to enable ARMv7 virtualization for current hypervisors 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <asm/armv7.h> 14 #include <asm/gic.h> 15 #include <asm/io.h> 16 17 unsigned long gic_dist_addr; 18 19 static unsigned int read_cpsr(void) 20 { 21 unsigned int reg; 22 23 asm volatile ("mrs %0, cpsr\n" : "=r" (reg)); 24 return reg; 25 } 26 27 static unsigned int read_id_pfr1(void) 28 { 29 unsigned int reg; 30 31 asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg)); 32 return reg; 33 } 34 35 static unsigned long get_gicd_base_address(void) 36 { 37 #ifdef CONFIG_ARM_GIC_BASE_ADDRESS 38 return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; 39 #else 40 unsigned midr; 41 unsigned periphbase; 42 43 /* check whether we are an Cortex-A15 or A7. 44 * The actual HYP switch should work with all CPUs supporting 45 * the virtualization extension, but we need the GIC address, 46 * which we know only for sure for those two CPUs. 47 */ 48 asm("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr)); 49 switch (midr & MIDR_PRIMARY_PART_MASK) { 50 case MIDR_CORTEX_A9_R0P1: 51 case MIDR_CORTEX_A15_R0P0: 52 case MIDR_CORTEX_A7_R0P0: 53 break; 54 default: 55 printf("nonsec: could not determine GIC address.\n"); 56 return -1; 57 } 58 59 /* get the GIC base address from the CBAR register */ 60 asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase)); 61 62 /* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to 63 * encode this). Bail out here since we cannot access this without 64 * enabling paging. 65 */ 66 if ((periphbase & 0xff) != 0) { 67 printf("nonsec: PERIPHBASE is above 4 GB, no access.\n"); 68 return -1; 69 } 70 71 return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET; 72 #endif 73 } 74 75 static void kick_secondary_cpus_gic(unsigned long gicdaddr) 76 { 77 /* kick all CPUs (except this one) by writing to GICD_SGIR */ 78 writel(1U << 24, gicdaddr + GICD_SGIR); 79 } 80 81 void __weak smp_kick_all_cpus(void) 82 { 83 kick_secondary_cpus_gic(gic_dist_addr); 84 } 85 86 int armv7_switch_hyp(void) 87 { 88 unsigned int reg; 89 90 /* check whether we are in HYP mode already */ 91 if ((read_cpsr() & 0x1f) == 0x1a) { 92 debug("CPU already in HYP mode\n"); 93 return 0; 94 } 95 96 /* check whether the CPU supports the virtualization extensions */ 97 reg = read_id_pfr1(); 98 if ((reg & CPUID_ARM_VIRT_MASK) != 1 << CPUID_ARM_VIRT_SHIFT) { 99 printf("HYP mode: Virtualization extensions not implemented.\n"); 100 return -1; 101 } 102 103 /* call the HYP switching code on this CPU also */ 104 _switch_to_hyp(); 105 106 if ((read_cpsr() & 0x1F) != 0x1a) { 107 printf("HYP mode: switch not successful.\n"); 108 return -1; 109 } 110 111 return 0; 112 } 113 114 int armv7_switch_nonsec(void) 115 { 116 unsigned int reg; 117 unsigned itlinesnr, i; 118 119 /* check whether the CPU supports the security extensions */ 120 reg = read_id_pfr1(); 121 if ((reg & 0xF0) == 0) { 122 printf("nonsec: Security extensions not implemented.\n"); 123 return -1; 124 } 125 126 /* the SCR register will be set directly in the monitor mode handler, 127 * according to the spec one should not tinker with it in secure state 128 * in SVC mode. Do not try to read it once in non-secure state, 129 * any access to it will trap. 130 */ 131 132 gic_dist_addr = get_gicd_base_address(); 133 if (gic_dist_addr == -1) 134 return -1; 135 136 /* enable the GIC distributor */ 137 writel(readl(gic_dist_addr + GICD_CTLR) | 0x03, 138 gic_dist_addr + GICD_CTLR); 139 140 /* TYPER[4:0] contains an encoded number of available interrupts */ 141 itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f; 142 143 /* set all bits in the GIC group registers to one to allow access 144 * from non-secure state. The first 32 interrupts are private per 145 * CPU and will be set later when enabling the GIC for each core 146 */ 147 for (i = 1; i <= itlinesnr; i++) 148 writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i); 149 150 smp_set_core_boot_addr((unsigned long)_smp_pen, -1); 151 smp_kick_all_cpus(); 152 153 /* call the non-sec switching code on this CPU also */ 154 _nonsec_init(); 155 156 return 0; 157 } 158