1 /* 2 * (C) Copyright 2013 3 * Andre Przywara, Linaro <andre.przywara@linaro.org> 4 * 5 * Routines to transition ARMv7 processors from secure into non-secure state 6 * and from non-secure SVC into HYP mode 7 * needed to enable ARMv7 virtualization for current hypervisors 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <asm/armv7.h> 14 #include <asm/gic.h> 15 #include <asm/io.h> 16 #include <asm/secure.h> 17 18 unsigned long gic_dist_addr; 19 20 static unsigned int read_id_pfr1(void) 21 { 22 unsigned int reg; 23 24 asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg)); 25 return reg; 26 } 27 28 static unsigned long get_gicd_base_address(void) 29 { 30 #ifdef CONFIG_ARM_GIC_BASE_ADDRESS 31 return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; 32 #else 33 unsigned periphbase; 34 35 /* get the GIC base address from the CBAR register */ 36 asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase)); 37 38 /* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to 39 * encode this). Bail out here since we cannot access this without 40 * enabling paging. 41 */ 42 if ((periphbase & 0xff) != 0) { 43 printf("nonsec: PERIPHBASE is above 4 GB, no access.\n"); 44 return -1; 45 } 46 47 return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET; 48 #endif 49 } 50 51 static void relocate_secure_section(void) 52 { 53 #ifdef CONFIG_ARMV7_SECURE_BASE 54 size_t sz = __secure_end - __secure_start; 55 56 memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz); 57 flush_dcache_range(CONFIG_ARMV7_SECURE_BASE, 58 CONFIG_ARMV7_SECURE_BASE + sz + 1); 59 invalidate_icache_all(); 60 #endif 61 } 62 63 static void kick_secondary_cpus_gic(unsigned long gicdaddr) 64 { 65 /* kick all CPUs (except this one) by writing to GICD_SGIR */ 66 writel(1U << 24, gicdaddr + GICD_SGIR); 67 } 68 69 void __weak smp_kick_all_cpus(void) 70 { 71 kick_secondary_cpus_gic(gic_dist_addr); 72 } 73 74 int armv7_init_nonsec(void) 75 { 76 unsigned int reg; 77 unsigned itlinesnr, i; 78 79 /* check whether the CPU supports the security extensions */ 80 reg = read_id_pfr1(); 81 if ((reg & 0xF0) == 0) { 82 printf("nonsec: Security extensions not implemented.\n"); 83 return -1; 84 } 85 86 /* the SCR register will be set directly in the monitor mode handler, 87 * according to the spec one should not tinker with it in secure state 88 * in SVC mode. Do not try to read it once in non-secure state, 89 * any access to it will trap. 90 */ 91 92 gic_dist_addr = get_gicd_base_address(); 93 if (gic_dist_addr == -1) 94 return -1; 95 96 /* enable the GIC distributor */ 97 writel(readl(gic_dist_addr + GICD_CTLR) | 0x03, 98 gic_dist_addr + GICD_CTLR); 99 100 /* TYPER[4:0] contains an encoded number of available interrupts */ 101 itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f; 102 103 /* set all bits in the GIC group registers to one to allow access 104 * from non-secure state. The first 32 interrupts are private per 105 * CPU and will be set later when enabling the GIC for each core 106 */ 107 for (i = 1; i <= itlinesnr; i++) 108 writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i); 109 110 #ifndef CONFIG_ARMV7_PSCI 111 smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1); 112 smp_kick_all_cpus(); 113 #endif 114 115 /* call the non-sec switching code on this CPU also */ 116 relocate_secure_section(); 117 secure_ram_addr(_nonsec_init)(); 118 return 0; 119 } 120