1 /* 2 * Copyright (C) 2014, STMicroelectronics - All Rights Reserved 3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <asm/io.h> 9 #include <asm/arch/stv0991_creg.h> 10 #include <asm/arch/stv0991_periph.h> 11 #include <asm/arch/hardware.h> 12 13 static struct stv0991_creg *const stv0991_creg = \ 14 (struct stv0991_creg *)CREG_BASE_ADDR; 15 16 int stv0991_pinmux_config(int peripheral) 17 { 18 switch (peripheral) { 19 case UART_GPIOC_30_31: 20 /* SSDA/SSCL pad muxing to UART Rx/Dx */ 21 writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) | 22 CFG_GPIOC_31_UART_RX, 23 &stv0991_creg->mux12); 24 writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) | 25 CFG_GPIOC_30_UART_TX, 26 &stv0991_creg->mux12); 27 /* SSDA/SSCL pad config to push pull*/ 28 writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) | 29 CFG_GPIOC_31_MODE_PP, 30 &stv0991_creg->cfg_pad6); 31 writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) | 32 CFG_GPIOC_30_MODE_HIGH, 33 &stv0991_creg->cfg_pad6); 34 break; 35 case UART_GPIOB_16_17: 36 /* ethernet rx_6/7 to UART Rx/Dx */ 37 writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) | 38 CFG_GPIOB_17_UART_RX, 39 &stv0991_creg->mux7); 40 writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) | 41 CFG_GPIOB_16_UART_TX, 42 &stv0991_creg->mux7); 43 break; 44 case ETH_GPIOB_10_31_C_0_4: 45 writel(readl(&stv0991_creg->mux6) & 0x000000FF, 46 &stv0991_creg->mux6); 47 writel(0x00000000, &stv0991_creg->mux7); 48 writel(0x00000000, &stv0991_creg->mux8); 49 writel(readl(&stv0991_creg->mux9) & 0xFFF00000, 50 &stv0991_creg->mux9); 51 /* Ethernet Voltage configuration to 1.8V*/ 52 writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | 53 ETH_VDD_CFG, &stv0991_creg->vdd_pad1); 54 writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | 55 ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1); 56 57 break; 58 case QSPI_CS_CLK_PAD: 59 writel((readl(&stv0991_creg->mux13) & FLASH_CS_NC_MASK) | 60 CFG_FLASH_CS_NC, &stv0991_creg->mux13); 61 writel((readl(&stv0991_creg->mux13) & FLASH_CLK_MASK) | 62 CFG_FLASH_CLK, &stv0991_creg->mux13); 63 default: 64 break; 65 } 66 return 0; 67 } 68