1*9fa32b12SVikas Manocha /* 2*9fa32b12SVikas Manocha * (C) Copyright 2014 3*9fa32b12SVikas Manocha * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. 4*9fa32b12SVikas Manocha * 5*9fa32b12SVikas Manocha * SPDX-License-Identifier: GPL-2.0+ 6*9fa32b12SVikas Manocha */ 7*9fa32b12SVikas Manocha 8*9fa32b12SVikas Manocha #include <asm/io.h> 9*9fa32b12SVikas Manocha #include <asm/arch/stv0991_creg.h> 10*9fa32b12SVikas Manocha #include <asm/arch/stv0991_periph.h> 11*9fa32b12SVikas Manocha #include <asm/arch/hardware.h> 12*9fa32b12SVikas Manocha 13*9fa32b12SVikas Manocha static struct stv0991_creg *const stv0991_creg = \ 14*9fa32b12SVikas Manocha (struct stv0991_creg *)CREG_BASE_ADDR; 15*9fa32b12SVikas Manocha 16*9fa32b12SVikas Manocha int stv0991_pinmux_config(int peripheral) 17*9fa32b12SVikas Manocha { 18*9fa32b12SVikas Manocha switch (peripheral) { 19*9fa32b12SVikas Manocha case UART_GPIOC_30_31: 20*9fa32b12SVikas Manocha /* SSDA/SSCL pad muxing to UART Rx/Dx */ 21*9fa32b12SVikas Manocha writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) | 22*9fa32b12SVikas Manocha CFG_GPIOC_31_UART_RX, 23*9fa32b12SVikas Manocha &stv0991_creg->mux12); 24*9fa32b12SVikas Manocha writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) | 25*9fa32b12SVikas Manocha CFG_GPIOC_30_UART_TX, 26*9fa32b12SVikas Manocha &stv0991_creg->mux12); 27*9fa32b12SVikas Manocha /* SSDA/SSCL pad config to push pull*/ 28*9fa32b12SVikas Manocha writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) | 29*9fa32b12SVikas Manocha CFG_GPIOC_31_MODE_PP, 30*9fa32b12SVikas Manocha &stv0991_creg->cfg_pad6); 31*9fa32b12SVikas Manocha writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) | 32*9fa32b12SVikas Manocha CFG_GPIOC_30_MODE_HIGH, 33*9fa32b12SVikas Manocha &stv0991_creg->cfg_pad6); 34*9fa32b12SVikas Manocha break; 35*9fa32b12SVikas Manocha case UART_GPIOB_16_17: 36*9fa32b12SVikas Manocha /* ethernet rx_6/7 to UART Rx/Dx */ 37*9fa32b12SVikas Manocha writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) | 38*9fa32b12SVikas Manocha CFG_GPIOB_17_UART_RX, 39*9fa32b12SVikas Manocha &stv0991_creg->mux7); 40*9fa32b12SVikas Manocha writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) | 41*9fa32b12SVikas Manocha CFG_GPIOB_16_UART_TX, 42*9fa32b12SVikas Manocha &stv0991_creg->mux7); 43*9fa32b12SVikas Manocha break; 44*9fa32b12SVikas Manocha default: 45*9fa32b12SVikas Manocha break; 46*9fa32b12SVikas Manocha } 47*9fa32b12SVikas Manocha return 0; 48*9fa32b12SVikas Manocha } 49