1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 29fa32b12SVikas Manocha /* 33bc599c9SPatrice Chotard * Copyright (C) 2014, STMicroelectronics - All Rights Reserved 43bc599c9SPatrice Chotard * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. 59fa32b12SVikas Manocha */ 69fa32b12SVikas Manocha 79fa32b12SVikas Manocha #include <asm/io.h> 89fa32b12SVikas Manocha #include <asm/arch/stv0991_creg.h> 99fa32b12SVikas Manocha #include <asm/arch/stv0991_periph.h> 109fa32b12SVikas Manocha #include <asm/arch/hardware.h> 119fa32b12SVikas Manocha 129fa32b12SVikas Manocha static struct stv0991_creg *const stv0991_creg = \ 139fa32b12SVikas Manocha (struct stv0991_creg *)CREG_BASE_ADDR; 149fa32b12SVikas Manocha 159fa32b12SVikas Manocha int stv0991_pinmux_config(int peripheral) 169fa32b12SVikas Manocha { 179fa32b12SVikas Manocha switch (peripheral) { 189fa32b12SVikas Manocha case UART_GPIOC_30_31: 199fa32b12SVikas Manocha /* SSDA/SSCL pad muxing to UART Rx/Dx */ 209fa32b12SVikas Manocha writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) | 219fa32b12SVikas Manocha CFG_GPIOC_31_UART_RX, 229fa32b12SVikas Manocha &stv0991_creg->mux12); 239fa32b12SVikas Manocha writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) | 249fa32b12SVikas Manocha CFG_GPIOC_30_UART_TX, 259fa32b12SVikas Manocha &stv0991_creg->mux12); 269fa32b12SVikas Manocha /* SSDA/SSCL pad config to push pull*/ 279fa32b12SVikas Manocha writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) | 289fa32b12SVikas Manocha CFG_GPIOC_31_MODE_PP, 299fa32b12SVikas Manocha &stv0991_creg->cfg_pad6); 309fa32b12SVikas Manocha writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) | 319fa32b12SVikas Manocha CFG_GPIOC_30_MODE_HIGH, 329fa32b12SVikas Manocha &stv0991_creg->cfg_pad6); 339fa32b12SVikas Manocha break; 349fa32b12SVikas Manocha case UART_GPIOB_16_17: 359fa32b12SVikas Manocha /* ethernet rx_6/7 to UART Rx/Dx */ 369fa32b12SVikas Manocha writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) | 379fa32b12SVikas Manocha CFG_GPIOB_17_UART_RX, 389fa32b12SVikas Manocha &stv0991_creg->mux7); 399fa32b12SVikas Manocha writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) | 409fa32b12SVikas Manocha CFG_GPIOB_16_UART_TX, 419fa32b12SVikas Manocha &stv0991_creg->mux7); 429fa32b12SVikas Manocha break; 432ce4eaf4SVikas Manocha case ETH_GPIOB_10_31_C_0_4: 442ce4eaf4SVikas Manocha writel(readl(&stv0991_creg->mux6) & 0x000000FF, 452ce4eaf4SVikas Manocha &stv0991_creg->mux6); 462ce4eaf4SVikas Manocha writel(0x00000000, &stv0991_creg->mux7); 472ce4eaf4SVikas Manocha writel(0x00000000, &stv0991_creg->mux8); 482ce4eaf4SVikas Manocha writel(readl(&stv0991_creg->mux9) & 0xFFF00000, 492ce4eaf4SVikas Manocha &stv0991_creg->mux9); 502ce4eaf4SVikas Manocha /* Ethernet Voltage configuration to 1.8V*/ 512ce4eaf4SVikas Manocha writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | 522ce4eaf4SVikas Manocha ETH_VDD_CFG, &stv0991_creg->vdd_pad1); 532ce4eaf4SVikas Manocha writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | 542ce4eaf4SVikas Manocha ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1); 552ce4eaf4SVikas Manocha 562ce4eaf4SVikas Manocha break; 5754afb500SVikas Manocha case QSPI_CS_CLK_PAD: 5854afb500SVikas Manocha writel((readl(&stv0991_creg->mux13) & FLASH_CS_NC_MASK) | 5954afb500SVikas Manocha CFG_FLASH_CS_NC, &stv0991_creg->mux13); 6054afb500SVikas Manocha writel((readl(&stv0991_creg->mux13) & FLASH_CLK_MASK) | 6154afb500SVikas Manocha CFG_FLASH_CLK, &stv0991_creg->mux13); 629fa32b12SVikas Manocha default: 639fa32b12SVikas Manocha break; 649fa32b12SVikas Manocha } 659fa32b12SVikas Manocha return 0; 669fa32b12SVikas Manocha } 67