19fa32b12SVikas Manocha /* 29fa32b12SVikas Manocha * (C) Copyright 2014 39fa32b12SVikas Manocha * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. 49fa32b12SVikas Manocha * 59fa32b12SVikas Manocha * SPDX-License-Identifier: GPL-2.0+ 69fa32b12SVikas Manocha */ 79fa32b12SVikas Manocha 89fa32b12SVikas Manocha #include <asm/io.h> 99fa32b12SVikas Manocha #include <asm/arch/stv0991_creg.h> 109fa32b12SVikas Manocha #include <asm/arch/stv0991_periph.h> 119fa32b12SVikas Manocha #include <asm/arch/hardware.h> 129fa32b12SVikas Manocha 139fa32b12SVikas Manocha static struct stv0991_creg *const stv0991_creg = \ 149fa32b12SVikas Manocha (struct stv0991_creg *)CREG_BASE_ADDR; 159fa32b12SVikas Manocha 169fa32b12SVikas Manocha int stv0991_pinmux_config(int peripheral) 179fa32b12SVikas Manocha { 189fa32b12SVikas Manocha switch (peripheral) { 199fa32b12SVikas Manocha case UART_GPIOC_30_31: 209fa32b12SVikas Manocha /* SSDA/SSCL pad muxing to UART Rx/Dx */ 219fa32b12SVikas Manocha writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) | 229fa32b12SVikas Manocha CFG_GPIOC_31_UART_RX, 239fa32b12SVikas Manocha &stv0991_creg->mux12); 249fa32b12SVikas Manocha writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) | 259fa32b12SVikas Manocha CFG_GPIOC_30_UART_TX, 269fa32b12SVikas Manocha &stv0991_creg->mux12); 279fa32b12SVikas Manocha /* SSDA/SSCL pad config to push pull*/ 289fa32b12SVikas Manocha writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) | 299fa32b12SVikas Manocha CFG_GPIOC_31_MODE_PP, 309fa32b12SVikas Manocha &stv0991_creg->cfg_pad6); 319fa32b12SVikas Manocha writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) | 329fa32b12SVikas Manocha CFG_GPIOC_30_MODE_HIGH, 339fa32b12SVikas Manocha &stv0991_creg->cfg_pad6); 349fa32b12SVikas Manocha break; 359fa32b12SVikas Manocha case UART_GPIOB_16_17: 369fa32b12SVikas Manocha /* ethernet rx_6/7 to UART Rx/Dx */ 379fa32b12SVikas Manocha writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) | 389fa32b12SVikas Manocha CFG_GPIOB_17_UART_RX, 399fa32b12SVikas Manocha &stv0991_creg->mux7); 409fa32b12SVikas Manocha writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) | 419fa32b12SVikas Manocha CFG_GPIOB_16_UART_TX, 429fa32b12SVikas Manocha &stv0991_creg->mux7); 439fa32b12SVikas Manocha break; 44*2ce4eaf4SVikas Manocha case ETH_GPIOB_10_31_C_0_4: 45*2ce4eaf4SVikas Manocha writel(readl(&stv0991_creg->mux6) & 0x000000FF, 46*2ce4eaf4SVikas Manocha &stv0991_creg->mux6); 47*2ce4eaf4SVikas Manocha writel(0x00000000, &stv0991_creg->mux7); 48*2ce4eaf4SVikas Manocha writel(0x00000000, &stv0991_creg->mux8); 49*2ce4eaf4SVikas Manocha writel(readl(&stv0991_creg->mux9) & 0xFFF00000, 50*2ce4eaf4SVikas Manocha &stv0991_creg->mux9); 51*2ce4eaf4SVikas Manocha /* Ethernet Voltage configuration to 1.8V*/ 52*2ce4eaf4SVikas Manocha writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | 53*2ce4eaf4SVikas Manocha ETH_VDD_CFG, &stv0991_creg->vdd_pad1); 54*2ce4eaf4SVikas Manocha writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | 55*2ce4eaf4SVikas Manocha ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1); 56*2ce4eaf4SVikas Manocha 57*2ce4eaf4SVikas Manocha break; 589fa32b12SVikas Manocha default: 599fa32b12SVikas Manocha break; 609fa32b12SVikas Manocha } 619fa32b12SVikas Manocha return 0; 629fa32b12SVikas Manocha } 63