1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16#include <asm-offsets.h> 17#include <config.h> 18#include <asm/system.h> 19#include <linux/linkage.h> 20#include <asm/armv7.h> 21 22/************************************************************************* 23 * 24 * Startup Code (reset vector) 25 * 26 * Do important init only if we don't start from memory! 27 * Setup memory and board specific bits prior to relocation. 28 * Relocate armboot to ram. Setup stack. 29 * 30 *************************************************************************/ 31 32 .globl reset 33 .globl save_boot_params_ret 34#ifdef CONFIG_ARMV7_LPAE 35 .global switch_to_hypervisor_ret 36#endif 37 38reset: 39 /* Allow the board to save important registers */ 40 b save_boot_params 41save_boot_params_ret: 42#ifdef CONFIG_ARMV7_LPAE 43/* 44 * check for Hypervisor support 45 */ 46 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 47 and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits 48 cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT) 49 beq switch_to_hypervisor 50switch_to_hypervisor_ret: 51#endif 52 /* 53 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, 54 * except if in HYP mode already 55 */ 56 mrs r0, cpsr 57 and r1, r0, #0x1f @ mask mode bits 58 teq r1, #0x1a @ test for HYP mode 59 bicne r0, r0, #0x1f @ clear all mode bits 60 orrne r0, r0, #0x13 @ set SVC mode 61 orr r0, r0, #0xc0 @ disable FIQ and IRQ 62 msr cpsr,r0 63 64/* 65 * Setup vector: 66 * (OMAP4 spl TEXT_BASE is not 32 byte aligned. 67 * Continue to use ROM code vector only in OMAP4 spl) 68 */ 69#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) 70 /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */ 71 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register 72 bic r0, #CR_V @ V = 0 73 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register 74 75 /* Set vector address in CP15 VBAR register */ 76 ldr r0, =_start 77 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 78#endif 79 80 /* the mask ROM code should have PLL and others stable */ 81#ifndef CONFIG_SKIP_LOWLEVEL_INIT 82 bl cpu_init_cp15 83#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY 84 bl cpu_init_crit 85#endif 86#endif 87 88 bl _main 89 90/*------------------------------------------------------------------------------*/ 91 92ENTRY(c_runtime_cpu_setup) 93/* 94 * If I-cache is enabled invalidate it 95 */ 96#ifndef CONFIG_SYS_ICACHE_OFF 97 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 98 mcr p15, 0, r0, c7, c10, 4 @ DSB 99 mcr p15, 0, r0, c7, c5, 4 @ ISB 100#endif 101 102 bx lr 103 104ENDPROC(c_runtime_cpu_setup) 105 106/************************************************************************* 107 * 108 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) 109 * __attribute__((weak)); 110 * 111 * Stack pointer is not yet initialized at this moment 112 * Don't save anything to stack even if compiled with -O0 113 * 114 *************************************************************************/ 115ENTRY(save_boot_params) 116 b save_boot_params_ret @ back to my caller 117ENDPROC(save_boot_params) 118 .weak save_boot_params 119 120#ifdef CONFIG_ARMV7_LPAE 121ENTRY(switch_to_hypervisor) 122 b switch_to_hypervisor_ret 123ENDPROC(switch_to_hypervisor) 124 .weak switch_to_hypervisor 125#endif 126 127/************************************************************************* 128 * 129 * cpu_init_cp15 130 * 131 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless 132 * CONFIG_SYS_ICACHE_OFF is defined. 133 * 134 *************************************************************************/ 135ENTRY(cpu_init_cp15) 136 /* 137 * Invalidate L1 I/D 138 */ 139 mov r0, #0 @ set up for MCR 140 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 141 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 142 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 143 mcr p15, 0, r0, c7, c10, 4 @ DSB 144 mcr p15, 0, r0, c7, c5, 4 @ ISB 145 146 /* 147 * disable MMU stuff and caches 148 */ 149 mrc p15, 0, r0, c1, c0, 0 150 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 151 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 152 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 153 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB 154#ifdef CONFIG_SYS_ICACHE_OFF 155 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache 156#else 157 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache 158#endif 159 mcr p15, 0, r0, c1, c0, 0 160 161#ifdef CONFIG_ARM_ERRATA_716044 162 mrc p15, 0, r0, c1, c0, 0 @ read system control register 163 orr r0, r0, #1 << 11 @ set bit #11 164 mcr p15, 0, r0, c1, c0, 0 @ write system control register 165#endif 166 167#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072)) 168 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 169 orr r0, r0, #1 << 4 @ set bit #4 170 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 171#endif 172 173#ifdef CONFIG_ARM_ERRATA_743622 174 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 175 orr r0, r0, #1 << 6 @ set bit #6 176 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 177#endif 178 179#ifdef CONFIG_ARM_ERRATA_751472 180 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 181 orr r0, r0, #1 << 11 @ set bit #11 182 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 183#endif 184#ifdef CONFIG_ARM_ERRATA_761320 185 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 186 orr r0, r0, #1 << 21 @ set bit #21 187 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 188#endif 189 190 mov r5, lr @ Store my Caller 191 mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR) 192 mov r3, r1, lsr #20 @ get variant field 193 and r3, r3, #0xf @ r3 has CPU variant 194 and r4, r1, #0xf @ r4 has CPU revision 195 mov r2, r3, lsl #4 @ shift variant field for combined value 196 orr r2, r4, r2 @ r2 has combined CPU variant + revision 197 198#ifdef CONFIG_ARM_ERRATA_798870 199 cmp r2, #0x30 @ Applies to lower than R3p0 200 bge skip_errata_798870 @ skip if not affected rev 201 cmp r2, #0x20 @ Applies to including and above R2p0 202 blt skip_errata_798870 @ skip if not affected rev 203 204 mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg 205 orr r0, r0, #1 << 7 @ Enable hazard-detect timeout 206 push {r1-r5} @ Save the cpu info registers 207 bl v7_arch_cp15_set_l2aux_ctrl 208 isb @ Recommended ISB after l2actlr update 209 pop {r1-r5} @ Restore the cpu info - fall through 210skip_errata_798870: 211#endif 212 213#ifdef CONFIG_ARM_ERRATA_801819 214 cmp r2, #0x24 @ Applies to lt including R2p4 215 bgt skip_errata_801819 @ skip if not affected rev 216 cmp r2, #0x20 @ Applies to including and above R2p0 217 blt skip_errata_801819 @ skip if not affected rev 218 mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg 219 and r0, r0, #1 << 3 @ check REVIDR[3] 220 cmp r0, #1 << 3 221 beq skip_errata_801819 @ skip erratum if REVIDR[3] is set 222 223 mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register 224 orr r0, r0, #3 << 27 @ Disables streaming. All write-allocate 225 @ lines allocate in the L1 or L2 cache. 226 orr r0, r0, #3 << 25 @ Disables streaming. All write-allocate 227 @ lines allocate in the L1 cache. 228 push {r1-r5} @ Save the cpu info registers 229 bl v7_arch_cp15_set_acr 230 pop {r1-r5} @ Restore the cpu info - fall through 231skip_errata_801819: 232#endif 233 234#ifdef CONFIG_ARM_ERRATA_454179 235 cmp r2, #0x21 @ Only on < r2p1 236 bge skip_errata_454179 237 238 mrc p15, 0, r0, c1, c0, 1 @ Read ACR 239 orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits 240 push {r1-r5} @ Save the cpu info registers 241 bl v7_arch_cp15_set_acr 242 pop {r1-r5} @ Restore the cpu info - fall through 243 244skip_errata_454179: 245#endif 246 247#ifdef CONFIG_ARM_ERRATA_430973 248 cmp r2, #0x21 @ Only on < r2p1 249 bge skip_errata_430973 250 251 mrc p15, 0, r0, c1, c0, 1 @ Read ACR 252 orr r0, r0, #(0x1 << 6) @ Set IBE bit 253 push {r1-r5} @ Save the cpu info registers 254 bl v7_arch_cp15_set_acr 255 pop {r1-r5} @ Restore the cpu info - fall through 256 257skip_errata_430973: 258#endif 259 260#ifdef CONFIG_ARM_ERRATA_621766 261 cmp r2, #0x21 @ Only on < r2p1 262 bge skip_errata_621766 263 264 mrc p15, 0, r0, c1, c0, 1 @ Read ACR 265 orr r0, r0, #(0x1 << 5) @ Set L1NEON bit 266 push {r1-r5} @ Save the cpu info registers 267 bl v7_arch_cp15_set_acr 268 pop {r1-r5} @ Restore the cpu info - fall through 269 270skip_errata_621766: 271#endif 272 273#ifdef CONFIG_ARM_ERRATA_725233 274 cmp r2, #0x21 @ Only on < r2p1 (Cortex A8) 275 bge skip_errata_725233 276 277 mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR 278 orr r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable 279 push {r1-r5} @ Save the cpu info registers 280 bl v7_arch_cp15_set_l2aux_ctrl 281 pop {r1-r5} @ Restore the cpu info - fall through 282 283skip_errata_725233: 284#endif 285 286 mov pc, r5 @ back to my caller 287ENDPROC(cpu_init_cp15) 288 289#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ 290 !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) 291/************************************************************************* 292 * 293 * CPU_init_critical registers 294 * 295 * setup important registers 296 * setup memory timing 297 * 298 *************************************************************************/ 299ENTRY(cpu_init_crit) 300 /* 301 * Jump to board specific initialization... 302 * The Mask ROM will have already initialized 303 * basic memory. Go here to bump up clock rate and handle 304 * wake up conditions. 305 */ 306 b lowlevel_init @ go setup pll,mux,memory 307ENDPROC(cpu_init_crit) 308#endif 309