xref: /openbmc/u-boot/arch/arm/cpu/armv7/start.S (revision b1e6c4c3) 
1/*
2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
3 *
4 * Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
5 *
6 * Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003	Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 */
31
32#include <asm-offsets.h>
33#include <config.h>
34#include <version.h>
35#include <asm/system.h>
36#include <linux/linkage.h>
37
38.globl _start
39_start: b	reset
40	ldr	pc, _undefined_instruction
41	ldr	pc, _software_interrupt
42	ldr	pc, _prefetch_abort
43	ldr	pc, _data_abort
44	ldr	pc, _not_used
45	ldr	pc, _irq
46	ldr	pc, _fiq
47#ifdef CONFIG_SPL_BUILD
48_undefined_instruction: .word _undefined_instruction
49_software_interrupt:	.word _software_interrupt
50_prefetch_abort:	.word _prefetch_abort
51_data_abort:		.word _data_abort
52_not_used:		.word _not_used
53_irq:			.word _irq
54_fiq:			.word _fiq
55_pad:			.word 0x12345678 /* now 16*4=64 */
56#else
57_undefined_instruction: .word undefined_instruction
58_software_interrupt:	.word software_interrupt
59_prefetch_abort:	.word prefetch_abort
60_data_abort:		.word data_abort
61_not_used:		.word not_used
62_irq:			.word irq
63_fiq:			.word fiq
64_pad:			.word 0x12345678 /* now 16*4=64 */
65#endif	/* CONFIG_SPL_BUILD */
66
67.global _end_vect
68_end_vect:
69
70	.balignl 16,0xdeadbeef
71/*************************************************************************
72 *
73 * Startup Code (reset vector)
74 *
75 * do important init only if we don't start from memory!
76 * setup Memory and board specific bits prior to relocation.
77 * relocate armboot to ram
78 * setup stack
79 *
80 *************************************************************************/
81
82.globl _TEXT_BASE
83_TEXT_BASE:
84#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
85	.word	CONFIG_SPL_TEXT_BASE
86#else
87	.word	CONFIG_SYS_TEXT_BASE
88#endif
89
90/*
91 * These are defined in the board-specific linker script.
92 */
93.globl _bss_start_ofs
94_bss_start_ofs:
95	.word __bss_start - _start
96
97.globl _image_copy_end_ofs
98_image_copy_end_ofs:
99	.word __image_copy_end - _start
100
101.globl _bss_end_ofs
102_bss_end_ofs:
103	.word __bss_end - _start
104
105.globl _end_ofs
106_end_ofs:
107	.word _end - _start
108
109#ifdef CONFIG_USE_IRQ
110/* IRQ stack memory (calculated at run-time) */
111.globl IRQ_STACK_START
112IRQ_STACK_START:
113	.word	0x0badc0de
114
115/* IRQ stack memory (calculated at run-time) */
116.globl FIQ_STACK_START
117FIQ_STACK_START:
118	.word 0x0badc0de
119#endif
120
121/* IRQ stack memory (calculated at run-time) + 8 bytes */
122.globl IRQ_STACK_START_IN
123IRQ_STACK_START_IN:
124	.word	0x0badc0de
125
126/*
127 * the actual reset code
128 */
129
130reset:
131	bl	save_boot_params
132	/*
133	 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
134	 * except if in HYP mode already
135	 */
136	mrs	r0, cpsr
137	and	r1, r0, #0x1f		@ mask mode bits
138	teq	r1, #0x1a		@ test for HYP mode
139	bicne	r0, r0, #0x1f		@ clear all mode bits
140	orrne	r0, r0, #0x13		@ set SVC mode
141	orr	r0, r0, #0xc0		@ disable FIQ and IRQ
142	msr	cpsr,r0
143
144/*
145 * Setup vector:
146 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
147 * Continue to use ROM code vector only in OMAP4 spl)
148 */
149#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
150	/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
151	mrc	p15, 0, r0, c1, c0, 0	@ Read CP15 SCTRL Register
152	bic	r0, #CR_V		@ V = 0
153	mcr	p15, 0, r0, c1, c0, 0	@ Write CP15 SCTRL Register
154
155	/* Set vector address in CP15 VBAR register */
156	ldr	r0, =_start
157	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
158#endif
159
160	/* the mask ROM code should have PLL and others stable */
161#ifndef CONFIG_SKIP_LOWLEVEL_INIT
162	bl	cpu_init_cp15
163	bl	cpu_init_crit
164#endif
165
166	bl	_main
167
168/*------------------------------------------------------------------------------*/
169
170#ifndef CONFIG_SPL_BUILD
171/*
172 * void relocate_code(addr_moni)
173 *
174 * This function relocates the monitor code.
175 */
176ENTRY(relocate_code)
177	mov	r6, r0	/* save addr of destination */
178
179	adr	r0, _start
180	subs	r9, r6, r0		/* r9 <- relocation offset */
181	beq	relocate_done		/* skip relocation */
182	mov	r1, r6			/* r1 <- scratch for copy_loop */
183	ldr	r3, _image_copy_end_ofs
184	add	r2, r0, r3		/* r2 <- source end address	    */
185
186copy_loop:
187	ldmia	r0!, {r10-r11}		/* copy from source address [r0]    */
188	stmia	r1!, {r10-r11}		/* copy to   target address [r1]    */
189	cmp	r0, r2			/* until source end address [r2]    */
190	blo	copy_loop
191
192	/*
193	 * fix .rel.dyn relocations
194	 */
195	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
196	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
197	add	r10, r10, r0		/* r10 <- sym table in FLASH */
198	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
199	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
200	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
201	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
202fixloop:
203	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
204	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
205	ldr	r1, [r2, #4]
206	and	r7, r1, #0xff
207	cmp	r7, #23			/* relative fixup? */
208	beq	fixrel
209	cmp	r7, #2			/* absolute fixup? */
210	beq	fixabs
211	/* ignore unknown type of fixup */
212	b	fixnext
213fixabs:
214	/* absolute fix: set location to (offset) symbol value */
215	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
216	add	r1, r10, r1		/* r1 <- address of symbol in table */
217	ldr	r1, [r1, #4]		/* r1 <- symbol value */
218	add	r1, r1, r9		/* r1 <- relocated sym addr */
219	b	fixnext
220fixrel:
221	/* relative fix: increase location by offset */
222	ldr	r1, [r0]
223	add	r1, r1, r9
224fixnext:
225	str	r1, [r0]
226	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
227	cmp	r2, r3
228	blo	fixloop
229
230relocate_done:
231
232	bx	lr
233
234_rel_dyn_start_ofs:
235	.word __rel_dyn_start - _start
236_rel_dyn_end_ofs:
237	.word __rel_dyn_end - _start
238_dynsym_start_ofs:
239	.word __dynsym_start - _start
240ENDPROC(relocate_code)
241
242#endif
243
244ENTRY(c_runtime_cpu_setup)
245/*
246 * If I-cache is enabled invalidate it
247 */
248#ifndef CONFIG_SYS_ICACHE_OFF
249	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
250	mcr     p15, 0, r0, c7, c10, 4	@ DSB
251	mcr     p15, 0, r0, c7, c5, 4	@ ISB
252#endif
253/*
254 * Move vector table
255 */
256	/* Set vector address in CP15 VBAR register */
257	ldr     r0, =_start
258	mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
259
260	bx	lr
261
262ENDPROC(c_runtime_cpu_setup)
263
264/*************************************************************************
265 *
266 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
267 *	__attribute__((weak));
268 *
269 * Stack pointer is not yet initialized at this moment
270 * Don't save anything to stack even if compiled with -O0
271 *
272 *************************************************************************/
273ENTRY(save_boot_params)
274	bx	lr			@ back to my caller
275ENDPROC(save_boot_params)
276	.weak	save_boot_params
277
278/*************************************************************************
279 *
280 * cpu_init_cp15
281 *
282 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
283 * CONFIG_SYS_ICACHE_OFF is defined.
284 *
285 *************************************************************************/
286ENTRY(cpu_init_cp15)
287	/*
288	 * Invalidate L1 I/D
289	 */
290	mov	r0, #0			@ set up for MCR
291	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
292	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
293	mcr	p15, 0, r0, c7, c5, 6	@ invalidate BP array
294	mcr     p15, 0, r0, c7, c10, 4	@ DSB
295	mcr     p15, 0, r0, c7, c5, 4	@ ISB
296
297	/*
298	 * disable MMU stuff and caches
299	 */
300	mrc	p15, 0, r0, c1, c0, 0
301	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
302	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
303	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
304	orr	r0, r0, #0x00000800	@ set bit 11 (Z---) BTB
305#ifdef CONFIG_SYS_ICACHE_OFF
306	bic	r0, r0, #0x00001000	@ clear bit 12 (I) I-cache
307#else
308	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-cache
309#endif
310	mcr	p15, 0, r0, c1, c0, 0
311
312#ifdef CONFIG_ARM_ERRATA_716044
313	mrc	p15, 0, r0, c1, c0, 0	@ read system control register
314	orr	r0, r0, #1 << 11	@ set bit #11
315	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
316#endif
317
318#ifdef CONFIG_ARM_ERRATA_742230
319	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
320	orr	r0, r0, #1 << 4		@ set bit #4
321	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
322#endif
323
324#ifdef CONFIG_ARM_ERRATA_743622
325	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
326	orr	r0, r0, #1 << 6		@ set bit #6
327	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
328#endif
329
330#ifdef CONFIG_ARM_ERRATA_751472
331	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
332	orr	r0, r0, #1 << 11	@ set bit #11
333	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
334#endif
335
336	mov	pc, lr			@ back to my caller
337ENDPROC(cpu_init_cp15)
338
339#ifndef CONFIG_SKIP_LOWLEVEL_INIT
340/*************************************************************************
341 *
342 * CPU_init_critical registers
343 *
344 * setup important registers
345 * setup memory timing
346 *
347 *************************************************************************/
348ENTRY(cpu_init_crit)
349	/*
350	 * Jump to board specific initialization...
351	 * The Mask ROM will have already initialized
352	 * basic memory. Go here to bump up clock rate and handle
353	 * wake up conditions.
354	 */
355	b	lowlevel_init		@ go setup pll,mux,memory
356ENDPROC(cpu_init_crit)
357#endif
358
359#ifndef CONFIG_SPL_BUILD
360/*
361 *************************************************************************
362 *
363 * Interrupt handling
364 *
365 *************************************************************************
366 */
367@
368@ IRQ stack frame.
369@
370#define S_FRAME_SIZE	72
371
372#define S_OLD_R0	68
373#define S_PSR		64
374#define S_PC		60
375#define S_LR		56
376#define S_SP		52
377
378#define S_IP		48
379#define S_FP		44
380#define S_R10		40
381#define S_R9		36
382#define S_R8		32
383#define S_R7		28
384#define S_R6		24
385#define S_R5		20
386#define S_R4		16
387#define S_R3		12
388#define S_R2		8
389#define S_R1		4
390#define S_R0		0
391
392#define MODE_SVC 0x13
393#define I_BIT	 0x80
394
395/*
396 * use bad_save_user_regs for abort/prefetch/undef/swi ...
397 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
398 */
399
400	.macro	bad_save_user_regs
401	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current
402						@ user stack
403	stmia	sp, {r0 - r12}			@ Save user registers (now in
404						@ svc mode) r0-r12
405	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort
406						@ stack
407	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc
408						@ and cpsr (into parm regs)
409	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
410
411	add	r5, sp, #S_SP
412	mov	r1, lr
413	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
414	mov	r0, sp				@ save current stack into r0
415						@ (param register)
416	.endm
417
418	.macro	irq_save_user_regs
419	sub	sp, sp, #S_FRAME_SIZE
420	stmia	sp, {r0 - r12}			@ Calling r0-r12
421	add	r8, sp, #S_PC			@ !! R8 NEEDS to be saved !!
422						@ a reserved stack spot would
423						@ be good.
424	stmdb	r8, {sp, lr}^			@ Calling SP, LR
425	str	lr, [r8, #0]			@ Save calling PC
426	mrs	r6, spsr
427	str	r6, [r8, #4]			@ Save CPSR
428	str	r0, [r8, #8]			@ Save OLD_R0
429	mov	r0, sp
430	.endm
431
432	.macro	irq_restore_user_regs
433	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
434	mov	r0, r0
435	ldr	lr, [sp, #S_PC]			@ Get PC
436	add	sp, sp, #S_FRAME_SIZE
437	subs	pc, lr, #4			@ return & move spsr_svc into
438						@ cpsr
439	.endm
440
441	.macro get_bad_stack
442	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter
443						@ in banked mode)
444
445	str	lr, [r13]			@ save caller lr in position 0
446						@ of saved stack
447	mrs	lr, spsr			@ get the spsr
448	str	lr, [r13, #4]			@ save spsr in position 1 of
449						@ saved stack
450
451	mov	r13, #MODE_SVC			@ prepare SVC-Mode
452	@ msr	spsr_c, r13
453	msr	spsr, r13			@ switch modes, make sure
454						@ moves will execute
455	mov	lr, pc				@ capture return pc
456	movs	pc, lr				@ jump to next instruction &
457						@ switch modes.
458	.endm
459
460	.macro get_bad_stack_swi
461	sub	r13, r13, #4			@ space on current stack for
462						@ scratch reg.
463	str	r0, [r13]			@ save R0's value.
464	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
465						@ spots for abort stack
466	str	lr, [r0]			@ save caller lr in position 0
467						@ of saved stack
468	mrs	lr, spsr			@ get the spsr
469	str	lr, [r0, #4]			@ save spsr in position 1 of
470						@ saved stack
471	ldr	lr, [r0]			@ restore lr
472	ldr	r0, [r13]			@ restore r0
473	add	r13, r13, #4			@ pop stack entry
474	.endm
475
476	.macro get_irq_stack			@ setup IRQ stack
477	ldr	sp, IRQ_STACK_START
478	.endm
479
480	.macro get_fiq_stack			@ setup FIQ stack
481	ldr	sp, FIQ_STACK_START
482	.endm
483
484/*
485 * exception handlers
486 */
487	.align	5
488undefined_instruction:
489	get_bad_stack
490	bad_save_user_regs
491	bl	do_undefined_instruction
492
493	.align	5
494software_interrupt:
495	get_bad_stack_swi
496	bad_save_user_regs
497	bl	do_software_interrupt
498
499	.align	5
500prefetch_abort:
501	get_bad_stack
502	bad_save_user_regs
503	bl	do_prefetch_abort
504
505	.align	5
506data_abort:
507	get_bad_stack
508	bad_save_user_regs
509	bl	do_data_abort
510
511	.align	5
512not_used:
513	get_bad_stack
514	bad_save_user_regs
515	bl	do_not_used
516
517#ifdef CONFIG_USE_IRQ
518
519	.align	5
520irq:
521	get_irq_stack
522	irq_save_user_regs
523	bl	do_irq
524	irq_restore_user_regs
525
526	.align	5
527fiq:
528	get_fiq_stack
529	/* someone ought to write a more effective fiq_save_user_regs */
530	irq_save_user_regs
531	bl	do_fiq
532	irq_restore_user_regs
533
534#else
535
536	.align	5
537irq:
538	get_bad_stack
539	bad_save_user_regs
540	bl	do_irq
541
542	.align	5
543fiq:
544	get_bad_stack
545	bad_save_user_regs
546	bl	do_fiq
547
548#endif /* CONFIG_USE_IRQ */
549#endif /* CONFIG_SPL_BUILD */
550