1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * See file CREDITS for list of people who contributed to this 14 * project. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 */ 31 32#include <asm-offsets.h> 33#include <config.h> 34#include <version.h> 35#include <asm/system.h> 36#include <linux/linkage.h> 37 38.globl _start 39_start: b reset 40 ldr pc, _undefined_instruction 41 ldr pc, _software_interrupt 42 ldr pc, _prefetch_abort 43 ldr pc, _data_abort 44 ldr pc, _not_used 45 ldr pc, _irq 46 ldr pc, _fiq 47#ifdef CONFIG_SPL_BUILD 48_undefined_instruction: .word _undefined_instruction 49_software_interrupt: .word _software_interrupt 50_prefetch_abort: .word _prefetch_abort 51_data_abort: .word _data_abort 52_not_used: .word _not_used 53_irq: .word _irq 54_fiq: .word _fiq 55_pad: .word 0x12345678 /* now 16*4=64 */ 56#else 57_undefined_instruction: .word undefined_instruction 58_software_interrupt: .word software_interrupt 59_prefetch_abort: .word prefetch_abort 60_data_abort: .word data_abort 61_not_used: .word not_used 62_irq: .word irq 63_fiq: .word fiq 64_pad: .word 0x12345678 /* now 16*4=64 */ 65#endif /* CONFIG_SPL_BUILD */ 66 67.global _end_vect 68_end_vect: 69 70 .balignl 16,0xdeadbeef 71/************************************************************************* 72 * 73 * Startup Code (reset vector) 74 * 75 * do important init only if we don't start from memory! 76 * setup Memory and board specific bits prior to relocation. 77 * relocate armboot to ram 78 * setup stack 79 * 80 *************************************************************************/ 81 82.globl _TEXT_BASE 83_TEXT_BASE: 84 .word CONFIG_SYS_TEXT_BASE 85 86/* 87 * These are defined in the board-specific linker script. 88 */ 89.globl _bss_start_ofs 90_bss_start_ofs: 91 .word __bss_start - _start 92 93.global _image_copy_end_ofs 94_image_copy_end_ofs: 95 .word __image_copy_end - _start 96 97.globl _bss_end_ofs 98_bss_end_ofs: 99 .word __bss_end__ - _start 100 101.globl _end_ofs 102_end_ofs: 103 .word _end - _start 104 105#ifdef CONFIG_USE_IRQ 106/* IRQ stack memory (calculated at run-time) */ 107.globl IRQ_STACK_START 108IRQ_STACK_START: 109 .word 0x0badc0de 110 111/* IRQ stack memory (calculated at run-time) */ 112.globl FIQ_STACK_START 113FIQ_STACK_START: 114 .word 0x0badc0de 115#endif 116 117/* IRQ stack memory (calculated at run-time) + 8 bytes */ 118.globl IRQ_STACK_START_IN 119IRQ_STACK_START_IN: 120 .word 0x0badc0de 121 122/* 123 * the actual reset code 124 */ 125 126reset: 127 bl save_boot_params 128 /* 129 * set the cpu to SVC32 mode 130 */ 131 mrs r0, cpsr 132 bic r0, r0, #0x1f 133 orr r0, r0, #0xd3 134 msr cpsr,r0 135 136/* 137 * Setup vector: 138 * (OMAP4 spl TEXT_BASE is not 32 byte aligned. 139 * Continue to use ROM code vector only in OMAP4 spl) 140 */ 141#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) 142 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */ 143 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register 144 bic r0, #CR_V @ V = 0 145 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register 146 147 /* Set vector address in CP15 VBAR register */ 148 ldr r0, =_start 149 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 150#endif 151 152 /* the mask ROM code should have PLL and others stable */ 153#ifndef CONFIG_SKIP_LOWLEVEL_INIT 154 bl cpu_init_cp15 155 bl cpu_init_crit 156#endif 157 158/* Set stackpointer in internal RAM to call board_init_f */ 159call_board_init_f: 160 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 161 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 162 ldr r0,=0x00000000 163 bl board_init_f 164 165/*------------------------------------------------------------------------------*/ 166 167#ifndef CONFIG_SPL_BUILD 168/* 169 * void relocate_code (addr_sp, gd, addr_moni) 170 * 171 * This "function" does not return, instead it continues in RAM 172 * after relocating the monitor code. 173 * 174 */ 175ENTRY(relocate_code) 176 mov r4, r0 /* save addr_sp */ 177 mov r5, r1 /* save addr of gd */ 178 mov r6, r2 /* save addr of destination */ 179 180 /* Set up the stack */ 181stack_setup: 182 mov sp, r4 183 184 adr r0, _start 185 cmp r0, r6 186 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 187 beq clear_bss /* skip relocation */ 188 mov r1, r6 /* r1 <- scratch for copy_loop */ 189 ldr r3, _image_copy_end_ofs 190 add r2, r0, r3 /* r2 <- source end address */ 191 192copy_loop: 193 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 194 stmia r1!, {r9-r10} /* copy to target address [r1] */ 195 cmp r0, r2 /* until source end address [r2] */ 196 blo copy_loop 197 198 /* 199 * fix .rel.dyn relocations 200 */ 201 ldr r0, _TEXT_BASE /* r0 <- Text base */ 202 sub r9, r6, r0 /* r9 <- relocation offset */ 203 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 204 add r10, r10, r0 /* r10 <- sym table in FLASH */ 205 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 206 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 207 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 208 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 209fixloop: 210 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 211 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 212 ldr r1, [r2, #4] 213 and r7, r1, #0xff 214 cmp r7, #23 /* relative fixup? */ 215 beq fixrel 216 cmp r7, #2 /* absolute fixup? */ 217 beq fixabs 218 /* ignore unknown type of fixup */ 219 b fixnext 220fixabs: 221 /* absolute fix: set location to (offset) symbol value */ 222 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 223 add r1, r10, r1 /* r1 <- address of symbol in table */ 224 ldr r1, [r1, #4] /* r1 <- symbol value */ 225 add r1, r1, r9 /* r1 <- relocated sym addr */ 226 b fixnext 227fixrel: 228 /* relative fix: increase location by offset */ 229 ldr r1, [r0] 230 add r1, r1, r9 231fixnext: 232 str r1, [r0] 233 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 234 cmp r2, r3 235 blo fixloop 236 b clear_bss 237_rel_dyn_start_ofs: 238 .word __rel_dyn_start - _start 239_rel_dyn_end_ofs: 240 .word __rel_dyn_end - _start 241_dynsym_start_ofs: 242 .word __dynsym_start - _start 243 244clear_bss: 245 ldr r0, _bss_start_ofs 246 ldr r1, _bss_end_ofs 247 mov r4, r6 /* reloc addr */ 248 add r0, r0, r4 249 add r1, r1, r4 250 mov r2, #0x00000000 /* clear */ 251 252clbss_l:cmp r0, r1 /* clear loop... */ 253 bhs clbss_e /* if reached end of bss, exit */ 254 str r2, [r0] 255 add r0, r0, #4 256 b clbss_l 257clbss_e: 258 259/* 260 * We are done. Do not return, instead branch to second part of board 261 * initialization, now running from RAM. 262 */ 263jump_2_ram: 264/* 265 * If I-cache is enabled invalidate it 266 */ 267#ifndef CONFIG_SYS_ICACHE_OFF 268 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 269 mcr p15, 0, r0, c7, c10, 4 @ DSB 270 mcr p15, 0, r0, c7, c5, 4 @ ISB 271#endif 272/* 273 * Move vector table 274 */ 275#if !defined(CONFIG_TEGRA20) 276 /* Set vector address in CP15 VBAR register */ 277 ldr r0, =_start 278 add r0, r0, r9 279 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 280#endif /* !Tegra20 */ 281 282 ldr r0, _board_init_r_ofs 283 adr r1, _start 284 add lr, r0, r1 285 add lr, lr, r9 286 /* setup parameters for board_init_r */ 287 mov r0, r5 /* gd_t */ 288 mov r1, r6 /* dest_addr */ 289 /* jump to it ... */ 290 mov pc, lr 291 292_board_init_r_ofs: 293 .word board_init_r - _start 294ENDPROC(relocate_code) 295#endif 296 297/************************************************************************* 298 * 299 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) 300 * __attribute__((weak)); 301 * 302 * Stack pointer is not yet initialized at this moment 303 * Don't save anything to stack even if compiled with -O0 304 * 305 *************************************************************************/ 306ENTRY(save_boot_params) 307 bx lr @ back to my caller 308ENDPROC(save_boot_params) 309 .weak save_boot_params 310 311/************************************************************************* 312 * 313 * cpu_init_cp15 314 * 315 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless 316 * CONFIG_SYS_ICACHE_OFF is defined. 317 * 318 *************************************************************************/ 319ENTRY(cpu_init_cp15) 320 /* 321 * Invalidate L1 I/D 322 */ 323 mov r0, #0 @ set up for MCR 324 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 325 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 326 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 327 mcr p15, 0, r0, c7, c10, 4 @ DSB 328 mcr p15, 0, r0, c7, c5, 4 @ ISB 329 330 /* 331 * disable MMU stuff and caches 332 */ 333 mrc p15, 0, r0, c1, c0, 0 334 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 335 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 336 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 337 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB 338#ifdef CONFIG_SYS_ICACHE_OFF 339 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache 340#else 341 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache 342#endif 343 mcr p15, 0, r0, c1, c0, 0 344 mov pc, lr @ back to my caller 345ENDPROC(cpu_init_cp15) 346 347#ifndef CONFIG_SKIP_LOWLEVEL_INIT 348/************************************************************************* 349 * 350 * CPU_init_critical registers 351 * 352 * setup important registers 353 * setup memory timing 354 * 355 *************************************************************************/ 356ENTRY(cpu_init_crit) 357 /* 358 * Jump to board specific initialization... 359 * The Mask ROM will have already initialized 360 * basic memory. Go here to bump up clock rate and handle 361 * wake up conditions. 362 */ 363 b lowlevel_init @ go setup pll,mux,memory 364ENDPROC(cpu_init_crit) 365#endif 366 367#ifndef CONFIG_SPL_BUILD 368/* 369 ************************************************************************* 370 * 371 * Interrupt handling 372 * 373 ************************************************************************* 374 */ 375@ 376@ IRQ stack frame. 377@ 378#define S_FRAME_SIZE 72 379 380#define S_OLD_R0 68 381#define S_PSR 64 382#define S_PC 60 383#define S_LR 56 384#define S_SP 52 385 386#define S_IP 48 387#define S_FP 44 388#define S_R10 40 389#define S_R9 36 390#define S_R8 32 391#define S_R7 28 392#define S_R6 24 393#define S_R5 20 394#define S_R4 16 395#define S_R3 12 396#define S_R2 8 397#define S_R1 4 398#define S_R0 0 399 400#define MODE_SVC 0x13 401#define I_BIT 0x80 402 403/* 404 * use bad_save_user_regs for abort/prefetch/undef/swi ... 405 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 406 */ 407 408 .macro bad_save_user_regs 409 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current 410 @ user stack 411 stmia sp, {r0 - r12} @ Save user registers (now in 412 @ svc mode) r0-r12 413 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort 414 @ stack 415 ldmia r2, {r2 - r3} @ get values for "aborted" pc 416 @ and cpsr (into parm regs) 417 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 418 419 add r5, sp, #S_SP 420 mov r1, lr 421 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 422 mov r0, sp @ save current stack into r0 423 @ (param register) 424 .endm 425 426 .macro irq_save_user_regs 427 sub sp, sp, #S_FRAME_SIZE 428 stmia sp, {r0 - r12} @ Calling r0-r12 429 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! 430 @ a reserved stack spot would 431 @ be good. 432 stmdb r8, {sp, lr}^ @ Calling SP, LR 433 str lr, [r8, #0] @ Save calling PC 434 mrs r6, spsr 435 str r6, [r8, #4] @ Save CPSR 436 str r0, [r8, #8] @ Save OLD_R0 437 mov r0, sp 438 .endm 439 440 .macro irq_restore_user_regs 441 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 442 mov r0, r0 443 ldr lr, [sp, #S_PC] @ Get PC 444 add sp, sp, #S_FRAME_SIZE 445 subs pc, lr, #4 @ return & move spsr_svc into 446 @ cpsr 447 .endm 448 449 .macro get_bad_stack 450 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter 451 @ in banked mode) 452 453 str lr, [r13] @ save caller lr in position 0 454 @ of saved stack 455 mrs lr, spsr @ get the spsr 456 str lr, [r13, #4] @ save spsr in position 1 of 457 @ saved stack 458 459 mov r13, #MODE_SVC @ prepare SVC-Mode 460 @ msr spsr_c, r13 461 msr spsr, r13 @ switch modes, make sure 462 @ moves will execute 463 mov lr, pc @ capture return pc 464 movs pc, lr @ jump to next instruction & 465 @ switch modes. 466 .endm 467 468 .macro get_bad_stack_swi 469 sub r13, r13, #4 @ space on current stack for 470 @ scratch reg. 471 str r0, [r13] @ save R0's value. 472 ldr r0, IRQ_STACK_START_IN @ get data regions start 473 @ spots for abort stack 474 str lr, [r0] @ save caller lr in position 0 475 @ of saved stack 476 mrs r0, spsr @ get the spsr 477 str lr, [r0, #4] @ save spsr in position 1 of 478 @ saved stack 479 ldr r0, [r13] @ restore r0 480 add r13, r13, #4 @ pop stack entry 481 .endm 482 483 .macro get_irq_stack @ setup IRQ stack 484 ldr sp, IRQ_STACK_START 485 .endm 486 487 .macro get_fiq_stack @ setup FIQ stack 488 ldr sp, FIQ_STACK_START 489 .endm 490 491/* 492 * exception handlers 493 */ 494 .align 5 495undefined_instruction: 496 get_bad_stack 497 bad_save_user_regs 498 bl do_undefined_instruction 499 500 .align 5 501software_interrupt: 502 get_bad_stack_swi 503 bad_save_user_regs 504 bl do_software_interrupt 505 506 .align 5 507prefetch_abort: 508 get_bad_stack 509 bad_save_user_regs 510 bl do_prefetch_abort 511 512 .align 5 513data_abort: 514 get_bad_stack 515 bad_save_user_regs 516 bl do_data_abort 517 518 .align 5 519not_used: 520 get_bad_stack 521 bad_save_user_regs 522 bl do_not_used 523 524#ifdef CONFIG_USE_IRQ 525 526 .align 5 527irq: 528 get_irq_stack 529 irq_save_user_regs 530 bl do_irq 531 irq_restore_user_regs 532 533 .align 5 534fiq: 535 get_fiq_stack 536 /* someone ought to write a more effective fiq_save_user_regs */ 537 irq_save_user_regs 538 bl do_fiq 539 irq_restore_user_regs 540 541#else 542 543 .align 5 544irq: 545 get_bad_stack 546 bad_save_user_regs 547 bl do_irq 548 549 .align 5 550fiq: 551 get_bad_stack 552 bad_save_user_regs 553 bl do_fiq 554 555#endif /* CONFIG_USE_IRQ */ 556#endif /* CONFIG_SPL_BUILD */ 557