1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * See file CREDITS for list of people who contributed to this 14 * project. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 */ 31 32#include <asm-offsets.h> 33#include <config.h> 34#include <version.h> 35#include <asm/system.h> 36 37.globl _start 38_start: b reset 39 ldr pc, _undefined_instruction 40 ldr pc, _software_interrupt 41 ldr pc, _prefetch_abort 42 ldr pc, _data_abort 43 ldr pc, _not_used 44 ldr pc, _irq 45 ldr pc, _fiq 46#ifdef CONFIG_SPL_BUILD 47_undefined_instruction: .word _undefined_instruction 48_software_interrupt: .word _software_interrupt 49_prefetch_abort: .word _prefetch_abort 50_data_abort: .word _data_abort 51_not_used: .word _not_used 52_irq: .word _irq 53_fiq: .word _fiq 54_pad: .word 0x12345678 /* now 16*4=64 */ 55#else 56_undefined_instruction: .word undefined_instruction 57_software_interrupt: .word software_interrupt 58_prefetch_abort: .word prefetch_abort 59_data_abort: .word data_abort 60_not_used: .word not_used 61_irq: .word irq 62_fiq: .word fiq 63_pad: .word 0x12345678 /* now 16*4=64 */ 64#endif /* CONFIG_SPL_BUILD */ 65 66.global _end_vect 67_end_vect: 68 69 .balignl 16,0xdeadbeef 70/************************************************************************* 71 * 72 * Startup Code (reset vector) 73 * 74 * do important init only if we don't start from memory! 75 * setup Memory and board specific bits prior to relocation. 76 * relocate armboot to ram 77 * setup stack 78 * 79 *************************************************************************/ 80 81.globl _TEXT_BASE 82_TEXT_BASE: 83 .word CONFIG_SYS_TEXT_BASE 84 85#ifdef CONFIG_TEGRA2 86/* 87 * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s). 88 * U-Boot runs on the AVP first, setting things up for the CPU (PLLs, 89 * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU 90 * to pick up its reset vector, which points here. 91 */ 92.globl _armboot_start 93_armboot_start: 94 .word _start 95#endif 96 97/* 98 * These are defined in the board-specific linker script. 99 */ 100.globl _bss_start_ofs 101_bss_start_ofs: 102 .word __bss_start - _start 103 104.global _image_copy_end_ofs 105_image_copy_end_ofs: 106 .word __image_copy_end - _start 107 108.globl _bss_end_ofs 109_bss_end_ofs: 110 .word __bss_end__ - _start 111 112.globl _end_ofs 113_end_ofs: 114 .word _end - _start 115 116#ifdef CONFIG_USE_IRQ 117/* IRQ stack memory (calculated at run-time) */ 118.globl IRQ_STACK_START 119IRQ_STACK_START: 120 .word 0x0badc0de 121 122/* IRQ stack memory (calculated at run-time) */ 123.globl FIQ_STACK_START 124FIQ_STACK_START: 125 .word 0x0badc0de 126#endif 127 128/* IRQ stack memory (calculated at run-time) + 8 bytes */ 129.globl IRQ_STACK_START_IN 130IRQ_STACK_START_IN: 131 .word 0x0badc0de 132 133/* 134 * the actual reset code 135 */ 136 137reset: 138 bl save_boot_params 139 /* 140 * set the cpu to SVC32 mode 141 */ 142 mrs r0, cpsr 143 bic r0, r0, #0x1f 144 orr r0, r0, #0xd3 145 msr cpsr,r0 146 147/* 148 * Setup vector: 149 * (OMAP4 spl TEXT_BASE is not 32 byte aligned. 150 * Continue to use ROM code vector only in OMAP4 spl) 151 */ 152#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) 153 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */ 154 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register 155 bic r0, #CR_V @ V = 0 156 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register 157 158 /* Set vector address in CP15 VBAR register */ 159 ldr r0, =_start 160 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 161#endif 162 163 /* the mask ROM code should have PLL and others stable */ 164#ifndef CONFIG_SKIP_LOWLEVEL_INIT 165 bl cpu_init_crit 166#endif 167 168/* Set stackpointer in internal RAM to call board_init_f */ 169call_board_init_f: 170 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 171 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 172 ldr r0,=0x00000000 173 bl board_init_f 174 175/*------------------------------------------------------------------------------*/ 176 177/* 178 * void relocate_code (addr_sp, gd, addr_moni) 179 * 180 * This "function" does not return, instead it continues in RAM 181 * after relocating the monitor code. 182 * 183 */ 184 .globl relocate_code 185relocate_code: 186 mov r4, r0 /* save addr_sp */ 187 mov r5, r1 /* save addr of gd */ 188 mov r6, r2 /* save addr of destination */ 189 190 /* Set up the stack */ 191stack_setup: 192 mov sp, r4 193 194 adr r0, _start 195 cmp r0, r6 196 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 197 beq clear_bss /* skip relocation */ 198 mov r1, r6 /* r1 <- scratch for copy_loop */ 199 ldr r3, _image_copy_end_ofs 200 add r2, r0, r3 /* r2 <- source end address */ 201 202copy_loop: 203 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 204 stmia r1!, {r9-r10} /* copy to target address [r1] */ 205 cmp r0, r2 /* until source end address [r2] */ 206 blo copy_loop 207 208#ifndef CONFIG_SPL_BUILD 209 /* 210 * fix .rel.dyn relocations 211 */ 212 ldr r0, _TEXT_BASE /* r0 <- Text base */ 213 sub r9, r6, r0 /* r9 <- relocation offset */ 214 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 215 add r10, r10, r0 /* r10 <- sym table in FLASH */ 216 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 217 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 218 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 219 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 220fixloop: 221 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 222 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 223 ldr r1, [r2, #4] 224 and r7, r1, #0xff 225 cmp r7, #23 /* relative fixup? */ 226 beq fixrel 227 cmp r7, #2 /* absolute fixup? */ 228 beq fixabs 229 /* ignore unknown type of fixup */ 230 b fixnext 231fixabs: 232 /* absolute fix: set location to (offset) symbol value */ 233 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 234 add r1, r10, r1 /* r1 <- address of symbol in table */ 235 ldr r1, [r1, #4] /* r1 <- symbol value */ 236 add r1, r1, r9 /* r1 <- relocated sym addr */ 237 b fixnext 238fixrel: 239 /* relative fix: increase location by offset */ 240 ldr r1, [r0] 241 add r1, r1, r9 242fixnext: 243 str r1, [r0] 244 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 245 cmp r2, r3 246 blo fixloop 247 b clear_bss 248_rel_dyn_start_ofs: 249 .word __rel_dyn_start - _start 250_rel_dyn_end_ofs: 251 .word __rel_dyn_end - _start 252_dynsym_start_ofs: 253 .word __dynsym_start - _start 254 255#endif /* #ifndef CONFIG_SPL_BUILD */ 256 257clear_bss: 258#ifdef CONFIG_SPL_BUILD 259 /* No relocation for SPL */ 260 ldr r0, =__bss_start 261 ldr r1, =__bss_end__ 262#else 263 ldr r0, _bss_start_ofs 264 ldr r1, _bss_end_ofs 265 mov r4, r6 /* reloc addr */ 266 add r0, r0, r4 267 add r1, r1, r4 268#endif 269 mov r2, #0x00000000 /* clear */ 270 271clbss_l:str r2, [r0] /* clear loop... */ 272 add r0, r0, #4 273 cmp r0, r1 274 bne clbss_l 275 276/* 277 * We are done. Do not return, instead branch to second part of board 278 * initialization, now running from RAM. 279 */ 280jump_2_ram: 281/* 282 * If I-cache is enabled invalidate it 283 */ 284#ifndef CONFIG_SYS_ICACHE_OFF 285 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 286 mcr p15, 0, r0, c7, c10, 4 @ DSB 287 mcr p15, 0, r0, c7, c5, 4 @ ISB 288#endif 289 ldr r0, _board_init_r_ofs 290 adr r1, _start 291 add lr, r0, r1 292 add lr, lr, r9 293 /* setup parameters for board_init_r */ 294 mov r0, r5 /* gd_t */ 295 mov r1, r6 /* dest_addr */ 296 /* jump to it ... */ 297 mov pc, lr 298 299_board_init_r_ofs: 300 .word board_init_r - _start 301 302 303#ifndef CONFIG_SKIP_LOWLEVEL_INIT 304/************************************************************************* 305 * 306 * CPU_init_critical registers 307 * 308 * setup important registers 309 * setup memory timing 310 * 311 *************************************************************************/ 312cpu_init_crit: 313 /* 314 * Invalidate L1 I/D 315 */ 316 mov r0, #0 @ set up for MCR 317 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 318 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 319 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 320 mcr p15, 0, r0, c7, c10, 4 @ DSB 321 mcr p15, 0, r0, c7, c5, 4 @ ISB 322 323 /* 324 * disable MMU stuff and caches 325 */ 326 mrc p15, 0, r0, c1, c0, 0 327 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 328 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 329 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 330 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB 331#ifdef CONFIG_SYS_ICACHE_OFF 332 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache 333#else 334 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache 335#endif 336 mcr p15, 0, r0, c1, c0, 0 337 338 /* 339 * Jump to board specific initialization... 340 * The Mask ROM will have already initialized 341 * basic memory. Go here to bump up clock rate and handle 342 * wake up conditions. 343 */ 344 mov ip, lr @ persevere link reg across call 345 bl lowlevel_init @ go setup pll,mux,memory 346 mov lr, ip @ restore link 347 mov pc, lr @ back to my caller 348#endif 349 350#ifndef CONFIG_SPL_BUILD 351/* 352 ************************************************************************* 353 * 354 * Interrupt handling 355 * 356 ************************************************************************* 357 */ 358@ 359@ IRQ stack frame. 360@ 361#define S_FRAME_SIZE 72 362 363#define S_OLD_R0 68 364#define S_PSR 64 365#define S_PC 60 366#define S_LR 56 367#define S_SP 52 368 369#define S_IP 48 370#define S_FP 44 371#define S_R10 40 372#define S_R9 36 373#define S_R8 32 374#define S_R7 28 375#define S_R6 24 376#define S_R5 20 377#define S_R4 16 378#define S_R3 12 379#define S_R2 8 380#define S_R1 4 381#define S_R0 0 382 383#define MODE_SVC 0x13 384#define I_BIT 0x80 385 386/* 387 * use bad_save_user_regs for abort/prefetch/undef/swi ... 388 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 389 */ 390 391 .macro bad_save_user_regs 392 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current 393 @ user stack 394 stmia sp, {r0 - r12} @ Save user registers (now in 395 @ svc mode) r0-r12 396 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort 397 @ stack 398 ldmia r2, {r2 - r3} @ get values for "aborted" pc 399 @ and cpsr (into parm regs) 400 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 401 402 add r5, sp, #S_SP 403 mov r1, lr 404 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 405 mov r0, sp @ save current stack into r0 406 @ (param register) 407 .endm 408 409 .macro irq_save_user_regs 410 sub sp, sp, #S_FRAME_SIZE 411 stmia sp, {r0 - r12} @ Calling r0-r12 412 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! 413 @ a reserved stack spot would 414 @ be good. 415 stmdb r8, {sp, lr}^ @ Calling SP, LR 416 str lr, [r8, #0] @ Save calling PC 417 mrs r6, spsr 418 str r6, [r8, #4] @ Save CPSR 419 str r0, [r8, #8] @ Save OLD_R0 420 mov r0, sp 421 .endm 422 423 .macro irq_restore_user_regs 424 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 425 mov r0, r0 426 ldr lr, [sp, #S_PC] @ Get PC 427 add sp, sp, #S_FRAME_SIZE 428 subs pc, lr, #4 @ return & move spsr_svc into 429 @ cpsr 430 .endm 431 432 .macro get_bad_stack 433 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter 434 @ in banked mode) 435 436 str lr, [r13] @ save caller lr in position 0 437 @ of saved stack 438 mrs lr, spsr @ get the spsr 439 str lr, [r13, #4] @ save spsr in position 1 of 440 @ saved stack 441 442 mov r13, #MODE_SVC @ prepare SVC-Mode 443 @ msr spsr_c, r13 444 msr spsr, r13 @ switch modes, make sure 445 @ moves will execute 446 mov lr, pc @ capture return pc 447 movs pc, lr @ jump to next instruction & 448 @ switch modes. 449 .endm 450 451 .macro get_bad_stack_swi 452 sub r13, r13, #4 @ space on current stack for 453 @ scratch reg. 454 str r0, [r13] @ save R0's value. 455 ldr r0, IRQ_STACK_START_IN @ get data regions start 456 @ spots for abort stack 457 str lr, [r0] @ save caller lr in position 0 458 @ of saved stack 459 mrs r0, spsr @ get the spsr 460 str lr, [r0, #4] @ save spsr in position 1 of 461 @ saved stack 462 ldr r0, [r13] @ restore r0 463 add r13, r13, #4 @ pop stack entry 464 .endm 465 466 .macro get_irq_stack @ setup IRQ stack 467 ldr sp, IRQ_STACK_START 468 .endm 469 470 .macro get_fiq_stack @ setup FIQ stack 471 ldr sp, FIQ_STACK_START 472 .endm 473 474/* 475 * exception handlers 476 */ 477 .align 5 478undefined_instruction: 479 get_bad_stack 480 bad_save_user_regs 481 bl do_undefined_instruction 482 483 .align 5 484software_interrupt: 485 get_bad_stack_swi 486 bad_save_user_regs 487 bl do_software_interrupt 488 489 .align 5 490prefetch_abort: 491 get_bad_stack 492 bad_save_user_regs 493 bl do_prefetch_abort 494 495 .align 5 496data_abort: 497 get_bad_stack 498 bad_save_user_regs 499 bl do_data_abort 500 501 .align 5 502not_used: 503 get_bad_stack 504 bad_save_user_regs 505 bl do_not_used 506 507#ifdef CONFIG_USE_IRQ 508 509 .align 5 510irq: 511 get_irq_stack 512 irq_save_user_regs 513 bl do_irq 514 irq_restore_user_regs 515 516 .align 5 517fiq: 518 get_fiq_stack 519 /* someone ought to write a more effective fiq_save_user_regs */ 520 irq_save_user_regs 521 bl do_fiq 522 irq_restore_user_regs 523 524#else 525 526 .align 5 527irq: 528 get_bad_stack 529 bad_save_user_regs 530 bl do_irq 531 532 .align 5 533fiq: 534 get_bad_stack 535 bad_save_user_regs 536 bl do_fiq 537 538#endif /* CONFIG_USE_IRQ */ 539#endif /* CONFIG_SPL_BUILD */ 540