1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * See file CREDITS for list of people who contributed to this 14 * project. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 */ 31 32#include <asm-offsets.h> 33#include <config.h> 34#include <version.h> 35 36.globl _start 37_start: b reset 38 ldr pc, _undefined_instruction 39 ldr pc, _software_interrupt 40 ldr pc, _prefetch_abort 41 ldr pc, _data_abort 42 ldr pc, _not_used 43 ldr pc, _irq 44 ldr pc, _fiq 45 46_undefined_instruction: .word undefined_instruction 47_software_interrupt: .word software_interrupt 48_prefetch_abort: .word prefetch_abort 49_data_abort: .word data_abort 50_not_used: .word not_used 51_irq: .word irq 52_fiq: .word fiq 53_pad: .word 0x12345678 /* now 16*4=64 */ 54.global _end_vect 55_end_vect: 56 57 .balignl 16,0xdeadbeef 58/************************************************************************* 59 * 60 * Startup Code (reset vector) 61 * 62 * do important init only if we don't start from memory! 63 * setup Memory and board specific bits prior to relocation. 64 * relocate armboot to ram 65 * setup stack 66 * 67 *************************************************************************/ 68 69.globl _TEXT_BASE 70_TEXT_BASE: 71 .word CONFIG_SYS_TEXT_BASE 72 73/* 74 * These are defined in the board-specific linker script. 75 */ 76.globl _bss_start_ofs 77_bss_start_ofs: 78 .word __bss_start - _start 79 80.globl _bss_end_ofs 81_bss_end_ofs: 82 .word __bss_end__ - _start 83 84.globl _end_ofs 85_end_ofs: 86 .word _end - _start 87 88#ifdef CONFIG_USE_IRQ 89/* IRQ stack memory (calculated at run-time) */ 90.globl IRQ_STACK_START 91IRQ_STACK_START: 92 .word 0x0badc0de 93 94/* IRQ stack memory (calculated at run-time) */ 95.globl FIQ_STACK_START 96FIQ_STACK_START: 97 .word 0x0badc0de 98#endif 99 100/* IRQ stack memory (calculated at run-time) + 8 bytes */ 101.globl IRQ_STACK_START_IN 102IRQ_STACK_START_IN: 103 .word 0x0badc0de 104 105/* 106 * the actual reset code 107 */ 108 109reset: 110 /* 111 * set the cpu to SVC32 mode 112 */ 113 mrs r0, cpsr 114 bic r0, r0, #0x1f 115 orr r0, r0, #0xd3 116 msr cpsr,r0 117 118#if (CONFIG_OMAP34XX) 119 /* Copy vectors to mask ROM indirect addr */ 120 adr r0, _start @ r0 <- current position of code 121 add r0, r0, #4 @ skip reset vector 122 mov r2, #64 @ r2 <- size to copy 123 add r2, r0, r2 @ r2 <- source end address 124 mov r1, #SRAM_OFFSET0 @ build vect addr 125 mov r3, #SRAM_OFFSET1 126 add r1, r1, r3 127 mov r3, #SRAM_OFFSET2 128 add r1, r1, r3 129next: 130 ldmia r0!, {r3 - r10} @ copy from source address [r0] 131 stmia r1!, {r3 - r10} @ copy to target address [r1] 132 cmp r0, r2 @ until source end address [r2] 133 bne next @ loop until equal */ 134#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) 135 /* No need to copy/exec the clock code - DPLL adjust already done 136 * in NAND/oneNAND Boot. 137 */ 138 bl cpy_clk_code @ put dpll adjust code behind vectors 139#endif /* NAND Boot */ 140#endif 141 /* the mask ROM code should have PLL and others stable */ 142#ifndef CONFIG_SKIP_LOWLEVEL_INIT 143 bl cpu_init_crit 144#endif 145 146/* Set stackpointer in internal RAM to call board_init_f */ 147call_board_init_f: 148 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 149 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 150 ldr r0,=0x00000000 151 bl board_init_f 152 153/*------------------------------------------------------------------------------*/ 154 155/* 156 * void relocate_code (addr_sp, gd, addr_moni) 157 * 158 * This "function" does not return, instead it continues in RAM 159 * after relocating the monitor code. 160 * 161 */ 162 .globl relocate_code 163relocate_code: 164 mov r4, r0 /* save addr_sp */ 165 mov r5, r1 /* save addr of gd */ 166 mov r6, r2 /* save addr of destination */ 167 168 /* Set up the stack */ 169stack_setup: 170 mov sp, r4 171 172 adr r0, _start 173#ifndef CONFIG_PRELOADER 174 cmp r0, r6 175 beq clear_bss /* skip relocation */ 176#endif 177 mov r1, r6 /* r1 <- scratch for copy_loop */ 178 ldr r3, _bss_start_ofs 179 add r2, r0, r3 /* r2 <- source end address */ 180 181copy_loop: 182 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 183 stmia r1!, {r9-r10} /* copy to target address [r1] */ 184 cmp r0, r2 /* until source end address [r2] */ 185 blo copy_loop 186 187#ifndef CONFIG_PRELOADER 188 /* 189 * fix .rel.dyn relocations 190 */ 191 ldr r0, _TEXT_BASE /* r0 <- Text base */ 192 sub r9, r6, r0 /* r9 <- relocation offset */ 193 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 194 add r10, r10, r0 /* r10 <- sym table in FLASH */ 195 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 196 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 197 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 198 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 199fixloop: 200 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 201 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 202 ldr r1, [r2, #4] 203 and r7, r1, #0xff 204 cmp r7, #23 /* relative fixup? */ 205 beq fixrel 206 cmp r7, #2 /* absolute fixup? */ 207 beq fixabs 208 /* ignore unknown type of fixup */ 209 b fixnext 210fixabs: 211 /* absolute fix: set location to (offset) symbol value */ 212 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 213 add r1, r10, r1 /* r1 <- address of symbol in table */ 214 ldr r1, [r1, #4] /* r1 <- symbol value */ 215 add r1, r1, r9 /* r1 <- relocated sym addr */ 216 b fixnext 217fixrel: 218 /* relative fix: increase location by offset */ 219 ldr r1, [r0] 220 add r1, r1, r9 221fixnext: 222 str r1, [r0] 223 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 224 cmp r2, r3 225 blo fixloop 226 227clear_bss: 228 ldr r0, _bss_start_ofs 229 ldr r1, _bss_end_ofs 230 mov r4, r6 /* reloc addr */ 231 add r0, r0, r4 232 add r1, r1, r4 233 mov r2, #0x00000000 /* clear */ 234 235clbss_l:str r2, [r0] /* clear loop... */ 236 add r0, r0, #4 237 cmp r0, r1 238 bne clbss_l 239#endif /* #ifndef CONFIG_PRELOADER */ 240 241/* 242 * We are done. Do not return, instead branch to second part of board 243 * initialization, now running from RAM. 244 */ 245jump_2_ram: 246 ldr r0, _board_init_r_ofs 247 adr r1, _start 248 add lr, r0, r1 249 add lr, lr, r9 250 /* setup parameters for board_init_r */ 251 mov r0, r5 /* gd_t */ 252 mov r1, r6 /* dest_addr */ 253 /* jump to it ... */ 254 mov pc, lr 255 256_board_init_r_ofs: 257 .word board_init_r - _start 258 259_rel_dyn_start_ofs: 260 .word __rel_dyn_start - _start 261_rel_dyn_end_ofs: 262 .word __rel_dyn_end - _start 263_dynsym_start_ofs: 264 .word __dynsym_start - _start 265 266/************************************************************************* 267 * 268 * CPU_init_critical registers 269 * 270 * setup important registers 271 * setup memory timing 272 * 273 *************************************************************************/ 274cpu_init_crit: 275 /* 276 * Invalidate L1 I/D 277 */ 278 mov r0, #0 @ set up for MCR 279 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 280 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 281 282 /* 283 * disable MMU stuff and caches 284 */ 285 mrc p15, 0, r0, c1, c0, 0 286 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 287 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 288 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 289 orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB 290 mcr p15, 0, r0, c1, c0, 0 291 292 /* 293 * Jump to board specific initialization... 294 * The Mask ROM will have already initialized 295 * basic memory. Go here to bump up clock rate and handle 296 * wake up conditions. 297 */ 298 mov ip, lr @ persevere link reg across call 299 bl lowlevel_init @ go setup pll,mux,memory 300 mov lr, ip @ restore link 301 mov pc, lr @ back to my caller 302/* 303 ************************************************************************* 304 * 305 * Interrupt handling 306 * 307 ************************************************************************* 308 */ 309@ 310@ IRQ stack frame. 311@ 312#define S_FRAME_SIZE 72 313 314#define S_OLD_R0 68 315#define S_PSR 64 316#define S_PC 60 317#define S_LR 56 318#define S_SP 52 319 320#define S_IP 48 321#define S_FP 44 322#define S_R10 40 323#define S_R9 36 324#define S_R8 32 325#define S_R7 28 326#define S_R6 24 327#define S_R5 20 328#define S_R4 16 329#define S_R3 12 330#define S_R2 8 331#define S_R1 4 332#define S_R0 0 333 334#define MODE_SVC 0x13 335#define I_BIT 0x80 336 337/* 338 * use bad_save_user_regs for abort/prefetch/undef/swi ... 339 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 340 */ 341 342 .macro bad_save_user_regs 343 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current 344 @ user stack 345 stmia sp, {r0 - r12} @ Save user registers (now in 346 @ svc mode) r0-r12 347 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort 348 @ stack 349 ldmia r2, {r2 - r3} @ get values for "aborted" pc 350 @ and cpsr (into parm regs) 351 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 352 353 add r5, sp, #S_SP 354 mov r1, lr 355 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 356 mov r0, sp @ save current stack into r0 357 @ (param register) 358 .endm 359 360 .macro irq_save_user_regs 361 sub sp, sp, #S_FRAME_SIZE 362 stmia sp, {r0 - r12} @ Calling r0-r12 363 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! 364 @ a reserved stack spot would 365 @ be good. 366 stmdb r8, {sp, lr}^ @ Calling SP, LR 367 str lr, [r8, #0] @ Save calling PC 368 mrs r6, spsr 369 str r6, [r8, #4] @ Save CPSR 370 str r0, [r8, #8] @ Save OLD_R0 371 mov r0, sp 372 .endm 373 374 .macro irq_restore_user_regs 375 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 376 mov r0, r0 377 ldr lr, [sp, #S_PC] @ Get PC 378 add sp, sp, #S_FRAME_SIZE 379 subs pc, lr, #4 @ return & move spsr_svc into 380 @ cpsr 381 .endm 382 383 .macro get_bad_stack 384 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter 385 @ in banked mode) 386 387 str lr, [r13] @ save caller lr in position 0 388 @ of saved stack 389 mrs lr, spsr @ get the spsr 390 str lr, [r13, #4] @ save spsr in position 1 of 391 @ saved stack 392 393 mov r13, #MODE_SVC @ prepare SVC-Mode 394 @ msr spsr_c, r13 395 msr spsr, r13 @ switch modes, make sure 396 @ moves will execute 397 mov lr, pc @ capture return pc 398 movs pc, lr @ jump to next instruction & 399 @ switch modes. 400 .endm 401 402 .macro get_bad_stack_swi 403 sub r13, r13, #4 @ space on current stack for 404 @ scratch reg. 405 str r0, [r13] @ save R0's value. 406 ldr r0, IRQ_STACK_START_IN @ get data regions start 407 @ spots for abort stack 408 str lr, [r0] @ save caller lr in position 0 409 @ of saved stack 410 mrs r0, spsr @ get the spsr 411 str lr, [r0, #4] @ save spsr in position 1 of 412 @ saved stack 413 ldr r0, [r13] @ restore r0 414 add r13, r13, #4 @ pop stack entry 415 .endm 416 417 .macro get_irq_stack @ setup IRQ stack 418 ldr sp, IRQ_STACK_START 419 .endm 420 421 .macro get_fiq_stack @ setup FIQ stack 422 ldr sp, FIQ_STACK_START 423 .endm 424 425/* 426 * exception handlers 427 */ 428 .align 5 429undefined_instruction: 430 get_bad_stack 431 bad_save_user_regs 432 bl do_undefined_instruction 433 434 .align 5 435software_interrupt: 436 get_bad_stack_swi 437 bad_save_user_regs 438 bl do_software_interrupt 439 440 .align 5 441prefetch_abort: 442 get_bad_stack 443 bad_save_user_regs 444 bl do_prefetch_abort 445 446 .align 5 447data_abort: 448 get_bad_stack 449 bad_save_user_regs 450 bl do_data_abort 451 452 .align 5 453not_used: 454 get_bad_stack 455 bad_save_user_regs 456 bl do_not_used 457 458#ifdef CONFIG_USE_IRQ 459 460 .align 5 461irq: 462 get_irq_stack 463 irq_save_user_regs 464 bl do_irq 465 irq_restore_user_regs 466 467 .align 5 468fiq: 469 get_fiq_stack 470 /* someone ought to write a more effective fiq_save_user_regs */ 471 irq_save_user_regs 472 bl do_fiq 473 irq_restore_user_regs 474 475#else 476 477 .align 5 478irq: 479 get_bad_stack 480 bad_save_user_regs 481 bl do_irq 482 483 .align 5 484fiq: 485 get_bad_stack 486 bad_save_user_regs 487 bl do_fiq 488 489#endif 490