1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * See file CREDITS for list of people who contributed to this 14 * project. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 */ 31 32#include <asm-offsets.h> 33#include <config.h> 34#include <version.h> 35#include <asm/system.h> 36#include <linux/linkage.h> 37 38.globl _start 39_start: b reset 40 ldr pc, _undefined_instruction 41 ldr pc, _software_interrupt 42 ldr pc, _prefetch_abort 43 ldr pc, _data_abort 44 ldr pc, _not_used 45 ldr pc, _irq 46 ldr pc, _fiq 47#ifdef CONFIG_SPL_BUILD 48_undefined_instruction: .word _undefined_instruction 49_software_interrupt: .word _software_interrupt 50_prefetch_abort: .word _prefetch_abort 51_data_abort: .word _data_abort 52_not_used: .word _not_used 53_irq: .word _irq 54_fiq: .word _fiq 55_pad: .word 0x12345678 /* now 16*4=64 */ 56#else 57_undefined_instruction: .word undefined_instruction 58_software_interrupt: .word software_interrupt 59_prefetch_abort: .word prefetch_abort 60_data_abort: .word data_abort 61_not_used: .word not_used 62_irq: .word irq 63_fiq: .word fiq 64_pad: .word 0x12345678 /* now 16*4=64 */ 65#endif /* CONFIG_SPL_BUILD */ 66 67.global _end_vect 68_end_vect: 69 70 .balignl 16,0xdeadbeef 71/************************************************************************* 72 * 73 * Startup Code (reset vector) 74 * 75 * do important init only if we don't start from memory! 76 * setup Memory and board specific bits prior to relocation. 77 * relocate armboot to ram 78 * setup stack 79 * 80 *************************************************************************/ 81 82.globl _TEXT_BASE 83_TEXT_BASE: 84 .word CONFIG_SYS_TEXT_BASE 85 86/* 87 * These are defined in the board-specific linker script. 88 */ 89.globl _bss_start_ofs 90_bss_start_ofs: 91 .word __bss_start - _start 92 93.global _image_copy_end_ofs 94_image_copy_end_ofs: 95 .word __image_copy_end - _start 96 97.globl _bss_end_ofs 98_bss_end_ofs: 99 .word __bss_end__ - _start 100 101.globl _end_ofs 102_end_ofs: 103 .word _end - _start 104 105#ifdef CONFIG_USE_IRQ 106/* IRQ stack memory (calculated at run-time) */ 107.globl IRQ_STACK_START 108IRQ_STACK_START: 109 .word 0x0badc0de 110 111/* IRQ stack memory (calculated at run-time) */ 112.globl FIQ_STACK_START 113FIQ_STACK_START: 114 .word 0x0badc0de 115#endif 116 117/* IRQ stack memory (calculated at run-time) + 8 bytes */ 118.globl IRQ_STACK_START_IN 119IRQ_STACK_START_IN: 120 .word 0x0badc0de 121 122/* 123 * the actual reset code 124 */ 125 126reset: 127 bl save_boot_params 128 /* 129 * set the cpu to SVC32 mode 130 */ 131 mrs r0, cpsr 132 bic r0, r0, #0x1f 133 orr r0, r0, #0xd3 134 msr cpsr,r0 135 136#if !defined(CONFIG_TEGRA2) 137/* 138 * Setup vector: 139 * (OMAP4 spl TEXT_BASE is not 32 byte aligned. 140 * Continue to use ROM code vector only in OMAP4 spl) 141 */ 142#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) 143 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */ 144 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register 145 bic r0, #CR_V @ V = 0 146 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register 147 148 /* Set vector address in CP15 VBAR register */ 149 ldr r0, =_start 150 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 151#endif 152#endif /* !Tegra2 */ 153 154 /* the mask ROM code should have PLL and others stable */ 155#ifndef CONFIG_SKIP_LOWLEVEL_INIT 156 bl cpu_init_cp15 157 bl cpu_init_crit 158#endif 159 160/* Set stackpointer in internal RAM to call board_init_f */ 161call_board_init_f: 162 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 163 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 164 ldr r0,=0x00000000 165 bl board_init_f 166 167/*------------------------------------------------------------------------------*/ 168 169/* 170 * void relocate_code (addr_sp, gd, addr_moni) 171 * 172 * This "function" does not return, instead it continues in RAM 173 * after relocating the monitor code. 174 * 175 */ 176ENTRY(relocate_code) 177 mov r4, r0 /* save addr_sp */ 178 mov r5, r1 /* save addr of gd */ 179 mov r6, r2 /* save addr of destination */ 180 181 /* Set up the stack */ 182stack_setup: 183 mov sp, r4 184 185 adr r0, _start 186 cmp r0, r6 187 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 188 beq clear_bss /* skip relocation */ 189 mov r1, r6 /* r1 <- scratch for copy_loop */ 190 ldr r3, _image_copy_end_ofs 191 add r2, r0, r3 /* r2 <- source end address */ 192 193copy_loop: 194 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 195 stmia r1!, {r9-r10} /* copy to target address [r1] */ 196 cmp r0, r2 /* until source end address [r2] */ 197 blo copy_loop 198 199#ifndef CONFIG_SPL_BUILD 200 /* 201 * fix .rel.dyn relocations 202 */ 203 ldr r0, _TEXT_BASE /* r0 <- Text base */ 204 sub r9, r6, r0 /* r9 <- relocation offset */ 205 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 206 add r10, r10, r0 /* r10 <- sym table in FLASH */ 207 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 208 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 209 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 210 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 211fixloop: 212 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 213 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 214 ldr r1, [r2, #4] 215 and r7, r1, #0xff 216 cmp r7, #23 /* relative fixup? */ 217 beq fixrel 218 cmp r7, #2 /* absolute fixup? */ 219 beq fixabs 220 /* ignore unknown type of fixup */ 221 b fixnext 222fixabs: 223 /* absolute fix: set location to (offset) symbol value */ 224 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 225 add r1, r10, r1 /* r1 <- address of symbol in table */ 226 ldr r1, [r1, #4] /* r1 <- symbol value */ 227 add r1, r1, r9 /* r1 <- relocated sym addr */ 228 b fixnext 229fixrel: 230 /* relative fix: increase location by offset */ 231 ldr r1, [r0] 232 add r1, r1, r9 233fixnext: 234 str r1, [r0] 235 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 236 cmp r2, r3 237 blo fixloop 238 b clear_bss 239_rel_dyn_start_ofs: 240 .word __rel_dyn_start - _start 241_rel_dyn_end_ofs: 242 .word __rel_dyn_end - _start 243_dynsym_start_ofs: 244 .word __dynsym_start - _start 245 246#endif /* #ifndef CONFIG_SPL_BUILD */ 247 248clear_bss: 249#ifdef CONFIG_SPL_BUILD 250 /* No relocation for SPL */ 251 ldr r0, =__bss_start 252 ldr r1, =__bss_end__ 253#else 254 ldr r0, _bss_start_ofs 255 ldr r1, _bss_end_ofs 256 mov r4, r6 /* reloc addr */ 257 add r0, r0, r4 258 add r1, r1, r4 259#endif 260 mov r2, #0x00000000 /* clear */ 261 262clbss_l:str r2, [r0] /* clear loop... */ 263 add r0, r0, #4 264 cmp r0, r1 265 bne clbss_l 266 267/* 268 * We are done. Do not return, instead branch to second part of board 269 * initialization, now running from RAM. 270 */ 271jump_2_ram: 272/* 273 * If I-cache is enabled invalidate it 274 */ 275#ifndef CONFIG_SYS_ICACHE_OFF 276 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 277 mcr p15, 0, r0, c7, c10, 4 @ DSB 278 mcr p15, 0, r0, c7, c5, 4 @ ISB 279#endif 280/* 281 * Move vector table 282 */ 283#if !defined(CONFIG_TEGRA2) 284#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) 285 /* Set vector address in CP15 VBAR register */ 286 ldr r0, =_start 287 add r0, r0, r9 288 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 289#endif 290#endif /* !Tegra2 */ 291 292 ldr r0, _board_init_r_ofs 293 adr r1, _start 294 add lr, r0, r1 295 add lr, lr, r9 296 /* setup parameters for board_init_r */ 297 mov r0, r5 /* gd_t */ 298 mov r1, r6 /* dest_addr */ 299 /* jump to it ... */ 300 mov pc, lr 301 302_board_init_r_ofs: 303 .word board_init_r - _start 304ENDPROC(relocate_code) 305 306/************************************************************************* 307 * 308 * cpu_init_cp15 309 * 310 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless 311 * CONFIG_SYS_ICACHE_OFF is defined. 312 * 313 *************************************************************************/ 314ENTRY(cpu_init_cp15) 315 /* 316 * Invalidate L1 I/D 317 */ 318 mov r0, #0 @ set up for MCR 319 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 320 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 321 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 322 mcr p15, 0, r0, c7, c10, 4 @ DSB 323 mcr p15, 0, r0, c7, c5, 4 @ ISB 324 325 /* 326 * disable MMU stuff and caches 327 */ 328 mrc p15, 0, r0, c1, c0, 0 329 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 330 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 331 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 332 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB 333#ifdef CONFIG_SYS_ICACHE_OFF 334 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache 335#else 336 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache 337#endif 338 mcr p15, 0, r0, c1, c0, 0 339 mov pc, lr @ back to my caller 340ENDPROC(cpu_init_cp15) 341 342#ifndef CONFIG_SKIP_LOWLEVEL_INIT 343/************************************************************************* 344 * 345 * CPU_init_critical registers 346 * 347 * setup important registers 348 * setup memory timing 349 * 350 *************************************************************************/ 351ENTRY(cpu_init_crit) 352 /* 353 * Jump to board specific initialization... 354 * The Mask ROM will have already initialized 355 * basic memory. Go here to bump up clock rate and handle 356 * wake up conditions. 357 */ 358 mov ip, lr @ persevere link reg across call 359 bl lowlevel_init @ go setup pll,mux,memory 360 mov lr, ip @ restore link 361 mov pc, lr @ back to my caller 362ENDPROC(cpu_init_crit) 363#endif 364 365#ifndef CONFIG_SPL_BUILD 366/* 367 ************************************************************************* 368 * 369 * Interrupt handling 370 * 371 ************************************************************************* 372 */ 373@ 374@ IRQ stack frame. 375@ 376#define S_FRAME_SIZE 72 377 378#define S_OLD_R0 68 379#define S_PSR 64 380#define S_PC 60 381#define S_LR 56 382#define S_SP 52 383 384#define S_IP 48 385#define S_FP 44 386#define S_R10 40 387#define S_R9 36 388#define S_R8 32 389#define S_R7 28 390#define S_R6 24 391#define S_R5 20 392#define S_R4 16 393#define S_R3 12 394#define S_R2 8 395#define S_R1 4 396#define S_R0 0 397 398#define MODE_SVC 0x13 399#define I_BIT 0x80 400 401/* 402 * use bad_save_user_regs for abort/prefetch/undef/swi ... 403 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 404 */ 405 406 .macro bad_save_user_regs 407 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current 408 @ user stack 409 stmia sp, {r0 - r12} @ Save user registers (now in 410 @ svc mode) r0-r12 411 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort 412 @ stack 413 ldmia r2, {r2 - r3} @ get values for "aborted" pc 414 @ and cpsr (into parm regs) 415 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 416 417 add r5, sp, #S_SP 418 mov r1, lr 419 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 420 mov r0, sp @ save current stack into r0 421 @ (param register) 422 .endm 423 424 .macro irq_save_user_regs 425 sub sp, sp, #S_FRAME_SIZE 426 stmia sp, {r0 - r12} @ Calling r0-r12 427 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! 428 @ a reserved stack spot would 429 @ be good. 430 stmdb r8, {sp, lr}^ @ Calling SP, LR 431 str lr, [r8, #0] @ Save calling PC 432 mrs r6, spsr 433 str r6, [r8, #4] @ Save CPSR 434 str r0, [r8, #8] @ Save OLD_R0 435 mov r0, sp 436 .endm 437 438 .macro irq_restore_user_regs 439 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 440 mov r0, r0 441 ldr lr, [sp, #S_PC] @ Get PC 442 add sp, sp, #S_FRAME_SIZE 443 subs pc, lr, #4 @ return & move spsr_svc into 444 @ cpsr 445 .endm 446 447 .macro get_bad_stack 448 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter 449 @ in banked mode) 450 451 str lr, [r13] @ save caller lr in position 0 452 @ of saved stack 453 mrs lr, spsr @ get the spsr 454 str lr, [r13, #4] @ save spsr in position 1 of 455 @ saved stack 456 457 mov r13, #MODE_SVC @ prepare SVC-Mode 458 @ msr spsr_c, r13 459 msr spsr, r13 @ switch modes, make sure 460 @ moves will execute 461 mov lr, pc @ capture return pc 462 movs pc, lr @ jump to next instruction & 463 @ switch modes. 464 .endm 465 466 .macro get_bad_stack_swi 467 sub r13, r13, #4 @ space on current stack for 468 @ scratch reg. 469 str r0, [r13] @ save R0's value. 470 ldr r0, IRQ_STACK_START_IN @ get data regions start 471 @ spots for abort stack 472 str lr, [r0] @ save caller lr in position 0 473 @ of saved stack 474 mrs r0, spsr @ get the spsr 475 str lr, [r0, #4] @ save spsr in position 1 of 476 @ saved stack 477 ldr r0, [r13] @ restore r0 478 add r13, r13, #4 @ pop stack entry 479 .endm 480 481 .macro get_irq_stack @ setup IRQ stack 482 ldr sp, IRQ_STACK_START 483 .endm 484 485 .macro get_fiq_stack @ setup FIQ stack 486 ldr sp, FIQ_STACK_START 487 .endm 488 489/* 490 * exception handlers 491 */ 492 .align 5 493undefined_instruction: 494 get_bad_stack 495 bad_save_user_regs 496 bl do_undefined_instruction 497 498 .align 5 499software_interrupt: 500 get_bad_stack_swi 501 bad_save_user_regs 502 bl do_software_interrupt 503 504 .align 5 505prefetch_abort: 506 get_bad_stack 507 bad_save_user_regs 508 bl do_prefetch_abort 509 510 .align 5 511data_abort: 512 get_bad_stack 513 bad_save_user_regs 514 bl do_data_abort 515 516 .align 5 517not_used: 518 get_bad_stack 519 bad_save_user_regs 520 bl do_not_used 521 522#ifdef CONFIG_USE_IRQ 523 524 .align 5 525irq: 526 get_irq_stack 527 irq_save_user_regs 528 bl do_irq 529 irq_restore_user_regs 530 531 .align 5 532fiq: 533 get_fiq_stack 534 /* someone ought to write a more effective fiq_save_user_regs */ 535 irq_save_user_regs 536 bl do_fiq 537 irq_restore_user_regs 538 539#else 540 541 .align 5 542irq: 543 get_bad_stack 544 bad_save_user_regs 545 bl do_irq 546 547 .align 5 548fiq: 549 get_bad_stack 550 bad_save_user_regs 551 bl do_fiq 552 553#endif /* CONFIG_USE_IRQ */ 554#endif /* CONFIG_SPL_BUILD */ 555