1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16#include <asm-offsets.h> 17#include <config.h> 18#include <version.h> 19#include <asm/system.h> 20#include <linux/linkage.h> 21 22.globl _start 23_start: b reset 24 ldr pc, _undefined_instruction 25 ldr pc, _software_interrupt 26 ldr pc, _prefetch_abort 27 ldr pc, _data_abort 28 ldr pc, _not_used 29 ldr pc, _irq 30 ldr pc, _fiq 31#ifdef CONFIG_SPL_BUILD 32_undefined_instruction: .word _undefined_instruction 33_software_interrupt: .word _software_interrupt 34_prefetch_abort: .word _prefetch_abort 35_data_abort: .word _data_abort 36_not_used: .word _not_used 37_irq: .word _irq 38_fiq: .word _fiq 39_pad: .word 0x12345678 /* now 16*4=64 */ 40#else 41_undefined_instruction: .word undefined_instruction 42_software_interrupt: .word software_interrupt 43_prefetch_abort: .word prefetch_abort 44_data_abort: .word data_abort 45_not_used: .word not_used 46_irq: .word irq 47_fiq: .word fiq 48_pad: .word 0x12345678 /* now 16*4=64 */ 49#endif /* CONFIG_SPL_BUILD */ 50 51.global _end_vect 52_end_vect: 53 54 .balignl 16,0xdeadbeef 55/************************************************************************* 56 * 57 * Startup Code (reset vector) 58 * 59 * do important init only if we don't start from memory! 60 * setup Memory and board specific bits prior to relocation. 61 * relocate armboot to ram 62 * setup stack 63 * 64 *************************************************************************/ 65 66.globl _TEXT_BASE 67_TEXT_BASE: 68#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 69 .word CONFIG_SPL_TEXT_BASE 70#else 71 .word CONFIG_SYS_TEXT_BASE 72#endif 73 74/* 75 * These are defined in the board-specific linker script. 76 */ 77.globl _bss_start_ofs 78_bss_start_ofs: 79 .word __bss_start - _start 80 81.globl _bss_end_ofs 82_bss_end_ofs: 83 .word __bss_end - _start 84 85.globl _end_ofs 86_end_ofs: 87 .word _end - _start 88 89#ifdef CONFIG_USE_IRQ 90/* IRQ stack memory (calculated at run-time) */ 91.globl IRQ_STACK_START 92IRQ_STACK_START: 93 .word 0x0badc0de 94 95/* IRQ stack memory (calculated at run-time) */ 96.globl FIQ_STACK_START 97FIQ_STACK_START: 98 .word 0x0badc0de 99#endif 100 101/* IRQ stack memory (calculated at run-time) + 8 bytes */ 102.globl IRQ_STACK_START_IN 103IRQ_STACK_START_IN: 104 .word 0x0badc0de 105 106/* 107 * the actual reset code 108 */ 109 110reset: 111 bl save_boot_params 112 /* 113 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, 114 * except if in HYP mode already 115 */ 116 mrs r0, cpsr 117 and r1, r0, #0x1f @ mask mode bits 118 teq r1, #0x1a @ test for HYP mode 119 bicne r0, r0, #0x1f @ clear all mode bits 120 orrne r0, r0, #0x13 @ set SVC mode 121 orr r0, r0, #0xc0 @ disable FIQ and IRQ 122 msr cpsr,r0 123 124/* 125 * Setup vector: 126 * (OMAP4 spl TEXT_BASE is not 32 byte aligned. 127 * Continue to use ROM code vector only in OMAP4 spl) 128 */ 129#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) 130 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */ 131 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register 132 bic r0, #CR_V @ V = 0 133 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register 134 135 /* Set vector address in CP15 VBAR register */ 136 ldr r0, =_start 137 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 138#endif 139 140 /* the mask ROM code should have PLL and others stable */ 141#ifndef CONFIG_SKIP_LOWLEVEL_INIT 142 bl cpu_init_cp15 143 bl cpu_init_crit 144#endif 145 146 bl _main 147 148/*------------------------------------------------------------------------------*/ 149 150ENTRY(c_runtime_cpu_setup) 151/* 152 * If I-cache is enabled invalidate it 153 */ 154#ifndef CONFIG_SYS_ICACHE_OFF 155 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 156 mcr p15, 0, r0, c7, c10, 4 @ DSB 157 mcr p15, 0, r0, c7, c5, 4 @ ISB 158#endif 159/* 160 * Move vector table 161 */ 162 /* Set vector address in CP15 VBAR register */ 163 ldr r0, =_start 164 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 165 166 bx lr 167 168ENDPROC(c_runtime_cpu_setup) 169 170/************************************************************************* 171 * 172 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) 173 * __attribute__((weak)); 174 * 175 * Stack pointer is not yet initialized at this moment 176 * Don't save anything to stack even if compiled with -O0 177 * 178 *************************************************************************/ 179ENTRY(save_boot_params) 180 bx lr @ back to my caller 181ENDPROC(save_boot_params) 182 .weak save_boot_params 183 184/************************************************************************* 185 * 186 * cpu_init_cp15 187 * 188 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless 189 * CONFIG_SYS_ICACHE_OFF is defined. 190 * 191 *************************************************************************/ 192ENTRY(cpu_init_cp15) 193 /* 194 * Invalidate L1 I/D 195 */ 196 mov r0, #0 @ set up for MCR 197 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 198 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 199 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 200 mcr p15, 0, r0, c7, c10, 4 @ DSB 201 mcr p15, 0, r0, c7, c5, 4 @ ISB 202 203 /* 204 * disable MMU stuff and caches 205 */ 206 mrc p15, 0, r0, c1, c0, 0 207 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 208 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 209 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 210 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB 211#ifdef CONFIG_SYS_ICACHE_OFF 212 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache 213#else 214 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache 215#endif 216 mcr p15, 0, r0, c1, c0, 0 217 218#ifdef CONFIG_ARM_ERRATA_716044 219 mrc p15, 0, r0, c1, c0, 0 @ read system control register 220 orr r0, r0, #1 << 11 @ set bit #11 221 mcr p15, 0, r0, c1, c0, 0 @ write system control register 222#endif 223 224#ifdef CONFIG_ARM_ERRATA_742230 225 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 226 orr r0, r0, #1 << 4 @ set bit #4 227 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 228#endif 229 230#ifdef CONFIG_ARM_ERRATA_743622 231 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 232 orr r0, r0, #1 << 6 @ set bit #6 233 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 234#endif 235 236#ifdef CONFIG_ARM_ERRATA_751472 237 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 238 orr r0, r0, #1 << 11 @ set bit #11 239 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 240#endif 241 242 mov pc, lr @ back to my caller 243ENDPROC(cpu_init_cp15) 244 245#ifndef CONFIG_SKIP_LOWLEVEL_INIT 246/************************************************************************* 247 * 248 * CPU_init_critical registers 249 * 250 * setup important registers 251 * setup memory timing 252 * 253 *************************************************************************/ 254ENTRY(cpu_init_crit) 255 /* 256 * Jump to board specific initialization... 257 * The Mask ROM will have already initialized 258 * basic memory. Go here to bump up clock rate and handle 259 * wake up conditions. 260 */ 261 b lowlevel_init @ go setup pll,mux,memory 262ENDPROC(cpu_init_crit) 263#endif 264 265#ifndef CONFIG_SPL_BUILD 266/* 267 ************************************************************************* 268 * 269 * Interrupt handling 270 * 271 ************************************************************************* 272 */ 273@ 274@ IRQ stack frame. 275@ 276#define S_FRAME_SIZE 72 277 278#define S_OLD_R0 68 279#define S_PSR 64 280#define S_PC 60 281#define S_LR 56 282#define S_SP 52 283 284#define S_IP 48 285#define S_FP 44 286#define S_R10 40 287#define S_R9 36 288#define S_R8 32 289#define S_R7 28 290#define S_R6 24 291#define S_R5 20 292#define S_R4 16 293#define S_R3 12 294#define S_R2 8 295#define S_R1 4 296#define S_R0 0 297 298#define MODE_SVC 0x13 299#define I_BIT 0x80 300 301/* 302 * use bad_save_user_regs for abort/prefetch/undef/swi ... 303 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 304 */ 305 306 .macro bad_save_user_regs 307 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current 308 @ user stack 309 stmia sp, {r0 - r12} @ Save user registers (now in 310 @ svc mode) r0-r12 311 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort 312 @ stack 313 ldmia r2, {r2 - r3} @ get values for "aborted" pc 314 @ and cpsr (into parm regs) 315 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 316 317 add r5, sp, #S_SP 318 mov r1, lr 319 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 320 mov r0, sp @ save current stack into r0 321 @ (param register) 322 .endm 323 324 .macro irq_save_user_regs 325 sub sp, sp, #S_FRAME_SIZE 326 stmia sp, {r0 - r12} @ Calling r0-r12 327 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! 328 @ a reserved stack spot would 329 @ be good. 330 stmdb r8, {sp, lr}^ @ Calling SP, LR 331 str lr, [r8, #0] @ Save calling PC 332 mrs r6, spsr 333 str r6, [r8, #4] @ Save CPSR 334 str r0, [r8, #8] @ Save OLD_R0 335 mov r0, sp 336 .endm 337 338 .macro irq_restore_user_regs 339 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 340 mov r0, r0 341 ldr lr, [sp, #S_PC] @ Get PC 342 add sp, sp, #S_FRAME_SIZE 343 subs pc, lr, #4 @ return & move spsr_svc into 344 @ cpsr 345 .endm 346 347 .macro get_bad_stack 348 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter 349 @ in banked mode) 350 351 str lr, [r13] @ save caller lr in position 0 352 @ of saved stack 353 mrs lr, spsr @ get the spsr 354 str lr, [r13, #4] @ save spsr in position 1 of 355 @ saved stack 356 357 mov r13, #MODE_SVC @ prepare SVC-Mode 358 @ msr spsr_c, r13 359 msr spsr, r13 @ switch modes, make sure 360 @ moves will execute 361 mov lr, pc @ capture return pc 362 movs pc, lr @ jump to next instruction & 363 @ switch modes. 364 .endm 365 366 .macro get_bad_stack_swi 367 sub r13, r13, #4 @ space on current stack for 368 @ scratch reg. 369 str r0, [r13] @ save R0's value. 370 ldr r0, IRQ_STACK_START_IN @ get data regions start 371 @ spots for abort stack 372 str lr, [r0] @ save caller lr in position 0 373 @ of saved stack 374 mrs lr, spsr @ get the spsr 375 str lr, [r0, #4] @ save spsr in position 1 of 376 @ saved stack 377 ldr lr, [r0] @ restore lr 378 ldr r0, [r13] @ restore r0 379 add r13, r13, #4 @ pop stack entry 380 .endm 381 382 .macro get_irq_stack @ setup IRQ stack 383 ldr sp, IRQ_STACK_START 384 .endm 385 386 .macro get_fiq_stack @ setup FIQ stack 387 ldr sp, FIQ_STACK_START 388 .endm 389 390/* 391 * exception handlers 392 */ 393 .align 5 394undefined_instruction: 395 get_bad_stack 396 bad_save_user_regs 397 bl do_undefined_instruction 398 399 .align 5 400software_interrupt: 401 get_bad_stack_swi 402 bad_save_user_regs 403 bl do_software_interrupt 404 405 .align 5 406prefetch_abort: 407 get_bad_stack 408 bad_save_user_regs 409 bl do_prefetch_abort 410 411 .align 5 412data_abort: 413 get_bad_stack 414 bad_save_user_regs 415 bl do_data_abort 416 417 .align 5 418not_used: 419 get_bad_stack 420 bad_save_user_regs 421 bl do_not_used 422 423#ifdef CONFIG_USE_IRQ 424 425 .align 5 426irq: 427 get_irq_stack 428 irq_save_user_regs 429 bl do_irq 430 irq_restore_user_regs 431 432 .align 5 433fiq: 434 get_fiq_stack 435 /* someone ought to write a more effective fiq_save_user_regs */ 436 irq_save_user_regs 437 bl do_fiq 438 irq_restore_user_regs 439 440#else 441 442 .align 5 443irq: 444 get_bad_stack 445 bad_save_user_regs 446 bl do_irq 447 448 .align 5 449fiq: 450 get_bad_stack 451 bad_save_user_regs 452 bl do_fiq 453 454#endif /* CONFIG_USE_IRQ */ 455#endif /* CONFIG_SPL_BUILD */ 456