1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 16#include <asm-offsets.h> 17#include <config.h> 18#include <version.h> 19#include <asm/system.h> 20#include <linux/linkage.h> 21 22.globl _start 23_start: b reset 24 ldr pc, _undefined_instruction 25 ldr pc, _software_interrupt 26 ldr pc, _prefetch_abort 27 ldr pc, _data_abort 28 ldr pc, _not_used 29 ldr pc, _irq 30 ldr pc, _fiq 31#ifdef CONFIG_SPL_BUILD 32_undefined_instruction: .word _undefined_instruction 33_software_interrupt: .word _software_interrupt 34_prefetch_abort: .word _prefetch_abort 35_data_abort: .word _data_abort 36_not_used: .word _not_used 37_irq: .word _irq 38_fiq: .word _fiq 39_pad: .word 0x12345678 /* now 16*4=64 */ 40#else 41.globl _undefined_instruction 42_undefined_instruction: .word undefined_instruction 43.globl _software_interrupt 44_software_interrupt: .word software_interrupt 45.globl _prefetch_abort 46_prefetch_abort: .word prefetch_abort 47.globl _data_abort 48_data_abort: .word data_abort 49.globl _not_used 50_not_used: .word not_used 51.globl _irq 52_irq: .word irq 53.globl _fiq 54_fiq: .word fiq 55_pad: .word 0x12345678 /* now 16*4=64 */ 56#endif /* CONFIG_SPL_BUILD */ 57 58.global _end_vect 59_end_vect: 60 61 .balignl 16,0xdeadbeef 62/************************************************************************* 63 * 64 * Startup Code (reset vector) 65 * 66 * do important init only if we don't start from memory! 67 * setup Memory and board specific bits prior to relocation. 68 * relocate armboot to ram 69 * setup stack 70 * 71 *************************************************************************/ 72 73#ifdef CONFIG_USE_IRQ 74/* IRQ stack memory (calculated at run-time) */ 75.globl IRQ_STACK_START 76IRQ_STACK_START: 77 .word 0x0badc0de 78 79/* IRQ stack memory (calculated at run-time) */ 80.globl FIQ_STACK_START 81FIQ_STACK_START: 82 .word 0x0badc0de 83#endif 84 85/* IRQ stack memory (calculated at run-time) + 8 bytes */ 86.globl IRQ_STACK_START_IN 87IRQ_STACK_START_IN: 88 .word 0x0badc0de 89 90/* 91 * the actual reset code 92 */ 93 94reset: 95 bl save_boot_params 96 /* 97 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, 98 * except if in HYP mode already 99 */ 100 mrs r0, cpsr 101 and r1, r0, #0x1f @ mask mode bits 102 teq r1, #0x1a @ test for HYP mode 103 bicne r0, r0, #0x1f @ clear all mode bits 104 orrne r0, r0, #0x13 @ set SVC mode 105 orr r0, r0, #0xc0 @ disable FIQ and IRQ 106 msr cpsr,r0 107 108/* 109 * Setup vector: 110 * (OMAP4 spl TEXT_BASE is not 32 byte aligned. 111 * Continue to use ROM code vector only in OMAP4 spl) 112 */ 113#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) 114 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */ 115 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register 116 bic r0, #CR_V @ V = 0 117 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register 118 119 /* Set vector address in CP15 VBAR register */ 120 ldr r0, =_start 121 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 122#endif 123 124 /* the mask ROM code should have PLL and others stable */ 125#ifndef CONFIG_SKIP_LOWLEVEL_INIT 126 bl cpu_init_cp15 127 bl cpu_init_crit 128#endif 129 130 bl _main 131 132/*------------------------------------------------------------------------------*/ 133 134ENTRY(c_runtime_cpu_setup) 135/* 136 * If I-cache is enabled invalidate it 137 */ 138#ifndef CONFIG_SYS_ICACHE_OFF 139 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 140 mcr p15, 0, r0, c7, c10, 4 @ DSB 141 mcr p15, 0, r0, c7, c5, 4 @ ISB 142#endif 143/* 144 * Move vector table 145 */ 146 /* Set vector address in CP15 VBAR register */ 147 ldr r0, =_start 148 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 149 150 bx lr 151 152ENDPROC(c_runtime_cpu_setup) 153 154/************************************************************************* 155 * 156 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) 157 * __attribute__((weak)); 158 * 159 * Stack pointer is not yet initialized at this moment 160 * Don't save anything to stack even if compiled with -O0 161 * 162 *************************************************************************/ 163ENTRY(save_boot_params) 164 bx lr @ back to my caller 165ENDPROC(save_boot_params) 166 .weak save_boot_params 167 168/************************************************************************* 169 * 170 * cpu_init_cp15 171 * 172 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless 173 * CONFIG_SYS_ICACHE_OFF is defined. 174 * 175 *************************************************************************/ 176ENTRY(cpu_init_cp15) 177 /* 178 * Invalidate L1 I/D 179 */ 180 mov r0, #0 @ set up for MCR 181 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 182 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 183 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 184 mcr p15, 0, r0, c7, c10, 4 @ DSB 185 mcr p15, 0, r0, c7, c5, 4 @ ISB 186 187 /* 188 * disable MMU stuff and caches 189 */ 190 mrc p15, 0, r0, c1, c0, 0 191 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 192 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 193 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 194 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB 195#ifdef CONFIG_SYS_ICACHE_OFF 196 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache 197#else 198 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache 199#endif 200 mcr p15, 0, r0, c1, c0, 0 201 202#ifdef CONFIG_ARM_ERRATA_716044 203 mrc p15, 0, r0, c1, c0, 0 @ read system control register 204 orr r0, r0, #1 << 11 @ set bit #11 205 mcr p15, 0, r0, c1, c0, 0 @ write system control register 206#endif 207 208#ifdef CONFIG_ARM_ERRATA_742230 209 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 210 orr r0, r0, #1 << 4 @ set bit #4 211 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 212#endif 213 214#ifdef CONFIG_ARM_ERRATA_743622 215 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 216 orr r0, r0, #1 << 6 @ set bit #6 217 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 218#endif 219 220#ifdef CONFIG_ARM_ERRATA_751472 221 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register 222 orr r0, r0, #1 << 11 @ set bit #11 223 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 224#endif 225 226 mov pc, lr @ back to my caller 227ENDPROC(cpu_init_cp15) 228 229#ifndef CONFIG_SKIP_LOWLEVEL_INIT 230/************************************************************************* 231 * 232 * CPU_init_critical registers 233 * 234 * setup important registers 235 * setup memory timing 236 * 237 *************************************************************************/ 238ENTRY(cpu_init_crit) 239 /* 240 * Jump to board specific initialization... 241 * The Mask ROM will have already initialized 242 * basic memory. Go here to bump up clock rate and handle 243 * wake up conditions. 244 */ 245 b lowlevel_init @ go setup pll,mux,memory 246ENDPROC(cpu_init_crit) 247#endif 248 249#ifndef CONFIG_SPL_BUILD 250/* 251 ************************************************************************* 252 * 253 * Interrupt handling 254 * 255 ************************************************************************* 256 */ 257@ 258@ IRQ stack frame. 259@ 260#define S_FRAME_SIZE 72 261 262#define S_OLD_R0 68 263#define S_PSR 64 264#define S_PC 60 265#define S_LR 56 266#define S_SP 52 267 268#define S_IP 48 269#define S_FP 44 270#define S_R10 40 271#define S_R9 36 272#define S_R8 32 273#define S_R7 28 274#define S_R6 24 275#define S_R5 20 276#define S_R4 16 277#define S_R3 12 278#define S_R2 8 279#define S_R1 4 280#define S_R0 0 281 282#define MODE_SVC 0x13 283#define I_BIT 0x80 284 285/* 286 * use bad_save_user_regs for abort/prefetch/undef/swi ... 287 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 288 */ 289 290 .macro bad_save_user_regs 291 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current 292 @ user stack 293 stmia sp, {r0 - r12} @ Save user registers (now in 294 @ svc mode) r0-r12 295 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort 296 @ stack 297 ldmia r2, {r2 - r3} @ get values for "aborted" pc 298 @ and cpsr (into parm regs) 299 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 300 301 add r5, sp, #S_SP 302 mov r1, lr 303 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 304 mov r0, sp @ save current stack into r0 305 @ (param register) 306 .endm 307 308 .macro irq_save_user_regs 309 sub sp, sp, #S_FRAME_SIZE 310 stmia sp, {r0 - r12} @ Calling r0-r12 311 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! 312 @ a reserved stack spot would 313 @ be good. 314 stmdb r8, {sp, lr}^ @ Calling SP, LR 315 str lr, [r8, #0] @ Save calling PC 316 mrs r6, spsr 317 str r6, [r8, #4] @ Save CPSR 318 str r0, [r8, #8] @ Save OLD_R0 319 mov r0, sp 320 .endm 321 322 .macro irq_restore_user_regs 323 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 324 mov r0, r0 325 ldr lr, [sp, #S_PC] @ Get PC 326 add sp, sp, #S_FRAME_SIZE 327 subs pc, lr, #4 @ return & move spsr_svc into 328 @ cpsr 329 .endm 330 331 .macro get_bad_stack 332 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter 333 @ in banked mode) 334 335 str lr, [r13] @ save caller lr in position 0 336 @ of saved stack 337 mrs lr, spsr @ get the spsr 338 str lr, [r13, #4] @ save spsr in position 1 of 339 @ saved stack 340 341 mov r13, #MODE_SVC @ prepare SVC-Mode 342 @ msr spsr_c, r13 343 msr spsr, r13 @ switch modes, make sure 344 @ moves will execute 345 mov lr, pc @ capture return pc 346 movs pc, lr @ jump to next instruction & 347 @ switch modes. 348 .endm 349 350 .macro get_bad_stack_swi 351 sub r13, r13, #4 @ space on current stack for 352 @ scratch reg. 353 str r0, [r13] @ save R0's value. 354 ldr r0, IRQ_STACK_START_IN @ get data regions start 355 @ spots for abort stack 356 str lr, [r0] @ save caller lr in position 0 357 @ of saved stack 358 mrs lr, spsr @ get the spsr 359 str lr, [r0, #4] @ save spsr in position 1 of 360 @ saved stack 361 ldr lr, [r0] @ restore lr 362 ldr r0, [r13] @ restore r0 363 add r13, r13, #4 @ pop stack entry 364 .endm 365 366 .macro get_irq_stack @ setup IRQ stack 367 ldr sp, IRQ_STACK_START 368 .endm 369 370 .macro get_fiq_stack @ setup FIQ stack 371 ldr sp, FIQ_STACK_START 372 .endm 373 374/* 375 * exception handlers 376 */ 377 .align 5 378undefined_instruction: 379 get_bad_stack 380 bad_save_user_regs 381 bl do_undefined_instruction 382 383 .align 5 384software_interrupt: 385 get_bad_stack_swi 386 bad_save_user_regs 387 bl do_software_interrupt 388 389 .align 5 390prefetch_abort: 391 get_bad_stack 392 bad_save_user_regs 393 bl do_prefetch_abort 394 395 .align 5 396data_abort: 397 get_bad_stack 398 bad_save_user_regs 399 bl do_data_abort 400 401 .align 5 402not_used: 403 get_bad_stack 404 bad_save_user_regs 405 bl do_not_used 406 407#ifdef CONFIG_USE_IRQ 408 409 .align 5 410irq: 411 get_irq_stack 412 irq_save_user_regs 413 bl do_irq 414 irq_restore_user_regs 415 416 .align 5 417fiq: 418 get_fiq_stack 419 /* someone ought to write a more effective fiq_save_user_regs */ 420 irq_save_user_regs 421 bl do_fiq 422 irq_restore_user_regs 423 424#else 425 426 .align 5 427irq: 428 get_bad_stack 429 bad_save_user_regs 430 bl do_irq 431 432 .align 5 433fiq: 434 get_bad_stack 435 bad_save_user_regs 436 bl do_fiq 437 438#endif /* CONFIG_USE_IRQ */ 439#endif /* CONFIG_SPL_BUILD */ 440