xref: /openbmc/u-boot/arch/arm/cpu/armv7/start.S (revision 3aa7a6a6) 
1/*
2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
3 *
4 * Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
5 *
6 * Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003	Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 */
31
32#include <asm-offsets.h>
33#include <config.h>
34#include <version.h>
35#include <asm/system.h>
36#include <linux/linkage.h>
37
38.globl _start
39_start: b	reset
40	ldr	pc, _undefined_instruction
41	ldr	pc, _software_interrupt
42	ldr	pc, _prefetch_abort
43	ldr	pc, _data_abort
44	ldr	pc, _not_used
45	ldr	pc, _irq
46	ldr	pc, _fiq
47#ifdef CONFIG_SPL_BUILD
48_undefined_instruction: .word _undefined_instruction
49_software_interrupt:	.word _software_interrupt
50_prefetch_abort:	.word _prefetch_abort
51_data_abort:		.word _data_abort
52_not_used:		.word _not_used
53_irq:			.word _irq
54_fiq:			.word _fiq
55_pad:			.word 0x12345678 /* now 16*4=64 */
56#else
57_undefined_instruction: .word undefined_instruction
58_software_interrupt:	.word software_interrupt
59_prefetch_abort:	.word prefetch_abort
60_data_abort:		.word data_abort
61_not_used:		.word not_used
62_irq:			.word irq
63_fiq:			.word fiq
64_pad:			.word 0x12345678 /* now 16*4=64 */
65#endif	/* CONFIG_SPL_BUILD */
66
67.global _end_vect
68_end_vect:
69
70	.balignl 16,0xdeadbeef
71/*************************************************************************
72 *
73 * Startup Code (reset vector)
74 *
75 * do important init only if we don't start from memory!
76 * setup Memory and board specific bits prior to relocation.
77 * relocate armboot to ram
78 * setup stack
79 *
80 *************************************************************************/
81
82.globl _TEXT_BASE
83_TEXT_BASE:
84	.word	CONFIG_SYS_TEXT_BASE
85
86/*
87 * These are defined in the board-specific linker script.
88 */
89.globl _bss_start_ofs
90_bss_start_ofs:
91	.word __bss_start - _start
92
93.global	_image_copy_end_ofs
94_image_copy_end_ofs:
95	.word 	__image_copy_end - _start
96
97.globl _bss_end_ofs
98_bss_end_ofs:
99	.word __bss_end__ - _start
100
101.globl _end_ofs
102_end_ofs:
103	.word _end - _start
104
105#ifdef CONFIG_USE_IRQ
106/* IRQ stack memory (calculated at run-time) */
107.globl IRQ_STACK_START
108IRQ_STACK_START:
109	.word	0x0badc0de
110
111/* IRQ stack memory (calculated at run-time) */
112.globl FIQ_STACK_START
113FIQ_STACK_START:
114	.word 0x0badc0de
115#endif
116
117/* IRQ stack memory (calculated at run-time) + 8 bytes */
118.globl IRQ_STACK_START_IN
119IRQ_STACK_START_IN:
120	.word	0x0badc0de
121
122/*
123 * the actual reset code
124 */
125
126reset:
127	bl	save_boot_params
128	/*
129	 * set the cpu to SVC32 mode
130	 */
131	mrs	r0, cpsr
132	bic	r0, r0, #0x1f
133	orr	r0, r0, #0xd3
134	msr	cpsr,r0
135
136/*
137 * Setup vector:
138 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
139 * Continue to use ROM code vector only in OMAP4 spl)
140 */
141#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
142	/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
143	mrc	p15, 0, r0, c1, c0, 0	@ Read CP15 SCTRL Register
144	bic	r0, #CR_V		@ V = 0
145	mcr	p15, 0, r0, c1, c0, 0	@ Write CP15 SCTRL Register
146
147	/* Set vector address in CP15 VBAR register */
148	ldr	r0, =_start
149	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
150#endif
151
152	/* the mask ROM code should have PLL and others stable */
153#ifndef CONFIG_SKIP_LOWLEVEL_INIT
154	bl	cpu_init_cp15
155	bl	cpu_init_crit
156#endif
157
158/* Set stackpointer in internal RAM to call board_init_f */
159call_board_init_f:
160	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
161	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
162	ldr	r0,=0x00000000
163	bl	board_init_f
164
165/*------------------------------------------------------------------------------*/
166
167/*
168 * void relocate_code (addr_sp, gd, addr_moni)
169 *
170 * This "function" does not return, instead it continues in RAM
171 * after relocating the monitor code.
172 *
173 */
174ENTRY(relocate_code)
175	mov	r4, r0	/* save addr_sp */
176	mov	r5, r1	/* save addr of gd */
177	mov	r6, r2	/* save addr of destination */
178
179	/* Set up the stack						    */
180stack_setup:
181	mov	sp, r4
182
183	adr	r0, _start
184	cmp	r0, r6
185	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
186	beq	clear_bss		/* skip relocation */
187	mov	r1, r6			/* r1 <- scratch for copy_loop */
188	ldr	r3, _image_copy_end_ofs
189	add	r2, r0, r3		/* r2 <- source end address	    */
190
191copy_loop:
192	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
193	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
194	cmp	r0, r2			/* until source end address [r2]    */
195	blo	copy_loop
196
197#ifndef CONFIG_SPL_BUILD
198	/*
199	 * fix .rel.dyn relocations
200	 */
201	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
202	sub	r9, r6, r0		/* r9 <- relocation offset */
203	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
204	add	r10, r10, r0		/* r10 <- sym table in FLASH */
205	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
206	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
207	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
208	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
209fixloop:
210	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
211	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
212	ldr	r1, [r2, #4]
213	and	r7, r1, #0xff
214	cmp	r7, #23			/* relative fixup? */
215	beq	fixrel
216	cmp	r7, #2			/* absolute fixup? */
217	beq	fixabs
218	/* ignore unknown type of fixup */
219	b	fixnext
220fixabs:
221	/* absolute fix: set location to (offset) symbol value */
222	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
223	add	r1, r10, r1		/* r1 <- address of symbol in table */
224	ldr	r1, [r1, #4]		/* r1 <- symbol value */
225	add	r1, r1, r9		/* r1 <- relocated sym addr */
226	b	fixnext
227fixrel:
228	/* relative fix: increase location by offset */
229	ldr	r1, [r0]
230	add	r1, r1, r9
231fixnext:
232	str	r1, [r0]
233	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
234	cmp	r2, r3
235	blo	fixloop
236	b	clear_bss
237_rel_dyn_start_ofs:
238	.word __rel_dyn_start - _start
239_rel_dyn_end_ofs:
240	.word __rel_dyn_end - _start
241_dynsym_start_ofs:
242	.word __dynsym_start - _start
243
244#endif	/* #ifndef CONFIG_SPL_BUILD */
245
246clear_bss:
247#ifdef CONFIG_SPL_BUILD
248	/* No relocation for SPL */
249	ldr	r0, =__bss_start
250	ldr	r1, =__bss_end__
251#else
252	ldr	r0, _bss_start_ofs
253	ldr	r1, _bss_end_ofs
254	mov	r4, r6			/* reloc addr */
255	add	r0, r0, r4
256	add	r1, r1, r4
257#endif
258	mov	r2, #0x00000000		/* clear			    */
259
260clbss_l:cmp	r0, r1			/* clear loop... */
261	bhs	clbss_e			/* if reached end of bss, exit */
262	str	r2, [r0]
263	add	r0, r0, #4
264	b	clbss_l
265clbss_e:
266
267/*
268 * We are done. Do not return, instead branch to second part of board
269 * initialization, now running from RAM.
270 */
271jump_2_ram:
272/*
273 * If I-cache is enabled invalidate it
274 */
275#ifndef CONFIG_SYS_ICACHE_OFF
276	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
277	mcr     p15, 0, r0, c7, c10, 4	@ DSB
278	mcr     p15, 0, r0, c7, c5, 4	@ ISB
279#endif
280/*
281 * Move vector table
282 */
283#if !defined(CONFIG_TEGRA20)
284#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
285	/* Set vector address in CP15 VBAR register */
286	ldr     r0, =_start
287	add     r0, r0, r9
288	mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
289#endif
290#endif /* !Tegra20 */
291
292	ldr	r0, _board_init_r_ofs
293	adr	r1, _start
294	add	lr, r0, r1
295	add	lr, lr, r9
296	/* setup parameters for board_init_r */
297	mov	r0, r5		/* gd_t */
298	mov	r1, r6		/* dest_addr */
299	/* jump to it ... */
300	mov	pc, lr
301
302_board_init_r_ofs:
303	.word board_init_r - _start
304ENDPROC(relocate_code)
305
306/*************************************************************************
307 *
308 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
309 *	__attribute__((weak));
310 *
311 * Stack pointer is not yet initialized at this moment
312 * Don't save anything to stack even if compiled with -O0
313 *
314 *************************************************************************/
315ENTRY(save_boot_params)
316	bx	lr			@ back to my caller
317ENDPROC(save_boot_params)
318	.weak	save_boot_params
319
320/*************************************************************************
321 *
322 * cpu_init_cp15
323 *
324 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
325 * CONFIG_SYS_ICACHE_OFF is defined.
326 *
327 *************************************************************************/
328ENTRY(cpu_init_cp15)
329	/*
330	 * Invalidate L1 I/D
331	 */
332	mov	r0, #0			@ set up for MCR
333	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
334	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
335	mcr	p15, 0, r0, c7, c5, 6	@ invalidate BP array
336	mcr     p15, 0, r0, c7, c10, 4	@ DSB
337	mcr     p15, 0, r0, c7, c5, 4	@ ISB
338
339	/*
340	 * disable MMU stuff and caches
341	 */
342	mrc	p15, 0, r0, c1, c0, 0
343	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
344	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
345	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
346	orr	r0, r0, #0x00000800	@ set bit 11 (Z---) BTB
347#ifdef CONFIG_SYS_ICACHE_OFF
348	bic	r0, r0, #0x00001000	@ clear bit 12 (I) I-cache
349#else
350	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-cache
351#endif
352	mcr	p15, 0, r0, c1, c0, 0
353	mov	pc, lr			@ back to my caller
354ENDPROC(cpu_init_cp15)
355
356#ifndef CONFIG_SKIP_LOWLEVEL_INIT
357/*************************************************************************
358 *
359 * CPU_init_critical registers
360 *
361 * setup important registers
362 * setup memory timing
363 *
364 *************************************************************************/
365ENTRY(cpu_init_crit)
366	/*
367	 * Jump to board specific initialization...
368	 * The Mask ROM will have already initialized
369	 * basic memory. Go here to bump up clock rate and handle
370	 * wake up conditions.
371	 */
372	mov	ip, lr			@ persevere link reg across call
373	bl	lowlevel_init		@ go setup pll,mux,memory
374	mov	lr, ip			@ restore link
375	mov	pc, lr			@ back to my caller
376ENDPROC(cpu_init_crit)
377#endif
378
379#ifndef CONFIG_SPL_BUILD
380/*
381 *************************************************************************
382 *
383 * Interrupt handling
384 *
385 *************************************************************************
386 */
387@
388@ IRQ stack frame.
389@
390#define S_FRAME_SIZE	72
391
392#define S_OLD_R0	68
393#define S_PSR		64
394#define S_PC		60
395#define S_LR		56
396#define S_SP		52
397
398#define S_IP		48
399#define S_FP		44
400#define S_R10		40
401#define S_R9		36
402#define S_R8		32
403#define S_R7		28
404#define S_R6		24
405#define S_R5		20
406#define S_R4		16
407#define S_R3		12
408#define S_R2		8
409#define S_R1		4
410#define S_R0		0
411
412#define MODE_SVC 0x13
413#define I_BIT	 0x80
414
415/*
416 * use bad_save_user_regs for abort/prefetch/undef/swi ...
417 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
418 */
419
420	.macro	bad_save_user_regs
421	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current
422						@ user stack
423	stmia	sp, {r0 - r12}			@ Save user registers (now in
424						@ svc mode) r0-r12
425	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort
426						@ stack
427	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc
428						@ and cpsr (into parm regs)
429	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
430
431	add	r5, sp, #S_SP
432	mov	r1, lr
433	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
434	mov	r0, sp				@ save current stack into r0
435						@ (param register)
436	.endm
437
438	.macro	irq_save_user_regs
439	sub	sp, sp, #S_FRAME_SIZE
440	stmia	sp, {r0 - r12}			@ Calling r0-r12
441	add	r8, sp, #S_PC			@ !! R8 NEEDS to be saved !!
442						@ a reserved stack spot would
443						@ be good.
444	stmdb	r8, {sp, lr}^			@ Calling SP, LR
445	str	lr, [r8, #0]			@ Save calling PC
446	mrs	r6, spsr
447	str	r6, [r8, #4]			@ Save CPSR
448	str	r0, [r8, #8]			@ Save OLD_R0
449	mov	r0, sp
450	.endm
451
452	.macro	irq_restore_user_regs
453	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
454	mov	r0, r0
455	ldr	lr, [sp, #S_PC]			@ Get PC
456	add	sp, sp, #S_FRAME_SIZE
457	subs	pc, lr, #4			@ return & move spsr_svc into
458						@ cpsr
459	.endm
460
461	.macro get_bad_stack
462	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter
463						@ in banked mode)
464
465	str	lr, [r13]			@ save caller lr in position 0
466						@ of saved stack
467	mrs	lr, spsr			@ get the spsr
468	str	lr, [r13, #4]			@ save spsr in position 1 of
469						@ saved stack
470
471	mov	r13, #MODE_SVC			@ prepare SVC-Mode
472	@ msr	spsr_c, r13
473	msr	spsr, r13			@ switch modes, make sure
474						@ moves will execute
475	mov	lr, pc				@ capture return pc
476	movs	pc, lr				@ jump to next instruction &
477						@ switch modes.
478	.endm
479
480	.macro get_bad_stack_swi
481	sub	r13, r13, #4			@ space on current stack for
482						@ scratch reg.
483	str	r0, [r13]			@ save R0's value.
484	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
485						@ spots for abort stack
486	str	lr, [r0]			@ save caller lr in position 0
487						@ of saved stack
488	mrs	r0, spsr			@ get the spsr
489	str	lr, [r0, #4]			@ save spsr in position 1 of
490						@ saved stack
491	ldr	r0, [r13]			@ restore r0
492	add	r13, r13, #4			@ pop stack entry
493	.endm
494
495	.macro get_irq_stack			@ setup IRQ stack
496	ldr	sp, IRQ_STACK_START
497	.endm
498
499	.macro get_fiq_stack			@ setup FIQ stack
500	ldr	sp, FIQ_STACK_START
501	.endm
502
503/*
504 * exception handlers
505 */
506	.align	5
507undefined_instruction:
508	get_bad_stack
509	bad_save_user_regs
510	bl	do_undefined_instruction
511
512	.align	5
513software_interrupt:
514	get_bad_stack_swi
515	bad_save_user_regs
516	bl	do_software_interrupt
517
518	.align	5
519prefetch_abort:
520	get_bad_stack
521	bad_save_user_regs
522	bl	do_prefetch_abort
523
524	.align	5
525data_abort:
526	get_bad_stack
527	bad_save_user_regs
528	bl	do_data_abort
529
530	.align	5
531not_used:
532	get_bad_stack
533	bad_save_user_regs
534	bl	do_not_used
535
536#ifdef CONFIG_USE_IRQ
537
538	.align	5
539irq:
540	get_irq_stack
541	irq_save_user_regs
542	bl	do_irq
543	irq_restore_user_regs
544
545	.align	5
546fiq:
547	get_fiq_stack
548	/* someone ought to write a more effective fiq_save_user_regs */
549	irq_save_user_regs
550	bl	do_fiq
551	irq_restore_user_regs
552
553#else
554
555	.align	5
556irq:
557	get_bad_stack
558	bad_save_user_regs
559	bl	do_irq
560
561	.align	5
562fiq:
563	get_bad_stack
564	bad_save_user_regs
565	bl	do_fiq
566
567#endif /* CONFIG_USE_IRQ */
568#endif /* CONFIG_SPL_BUILD */
569