1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * See file CREDITS for list of people who contributed to this 14 * project. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 */ 31 32#include <asm-offsets.h> 33#include <config.h> 34#include <version.h> 35 36.globl _start 37_start: b reset 38 ldr pc, _undefined_instruction 39 ldr pc, _software_interrupt 40 ldr pc, _prefetch_abort 41 ldr pc, _data_abort 42 ldr pc, _not_used 43 ldr pc, _irq 44 ldr pc, _fiq 45 46_undefined_instruction: .word undefined_instruction 47_software_interrupt: .word software_interrupt 48_prefetch_abort: .word prefetch_abort 49_data_abort: .word data_abort 50_not_used: .word not_used 51_irq: .word irq 52_fiq: .word fiq 53_pad: .word 0x12345678 /* now 16*4=64 */ 54.global _end_vect 55_end_vect: 56 57 .balignl 16,0xdeadbeef 58/************************************************************************* 59 * 60 * Startup Code (reset vector) 61 * 62 * do important init only if we don't start from memory! 63 * setup Memory and board specific bits prior to relocation. 64 * relocate armboot to ram 65 * setup stack 66 * 67 *************************************************************************/ 68 69.globl _TEXT_BASE 70_TEXT_BASE: 71 .word CONFIG_SYS_TEXT_BASE 72 73#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 74.globl _armboot_start 75_armboot_start: 76 .word _start 77#endif 78 79/* 80 * These are defined in the board-specific linker script. 81 */ 82.globl _bss_start_ofs 83_bss_start_ofs: 84 .word __bss_start - _start 85 86.globl _bss_end_ofs 87_bss_end_ofs: 88 .word _end - _start 89 90#ifdef CONFIG_USE_IRQ 91/* IRQ stack memory (calculated at run-time) */ 92.globl IRQ_STACK_START 93IRQ_STACK_START: 94 .word 0x0badc0de 95 96/* IRQ stack memory (calculated at run-time) */ 97.globl FIQ_STACK_START 98FIQ_STACK_START: 99 .word 0x0badc0de 100#endif 101 102#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 103/* IRQ stack memory (calculated at run-time) + 8 bytes */ 104.globl IRQ_STACK_START_IN 105IRQ_STACK_START_IN: 106 .word 0x0badc0de 107 108.globl _datarel_start_ofs 109_datarel_start_ofs: 110 .word __datarel_start - _start 111 112.globl _datarelrolocal_start_ofs 113_datarelrolocal_start_ofs: 114 .word __datarelrolocal_start - _start 115 116.globl _datarellocal_start_ofs 117_datarellocal_start_ofs: 118 .word __datarellocal_start - _start 119 120.globl _datarelro_start_ofs 121_datarelro_start_ofs: 122 .word __datarelro_start - _start 123 124.globl _got_start_ofs 125_got_start_ofs: 126 .word __got_start - _start 127 128.globl _got_end_Ofs 129_got_end_ofs: 130 .word __got_end - _start 131 132/* 133 * the actual reset code 134 */ 135 136reset: 137 /* 138 * set the cpu to SVC32 mode 139 */ 140 mrs r0, cpsr 141 bic r0, r0, #0x1f 142 orr r0, r0, #0xd3 143 msr cpsr,r0 144 145#if (CONFIG_OMAP34XX) 146 /* Copy vectors to mask ROM indirect addr */ 147 adr r0, _start @ r0 <- current position of code 148 add r0, r0, #4 @ skip reset vector 149 mov r2, #64 @ r2 <- size to copy 150 add r2, r0, r2 @ r2 <- source end address 151 mov r1, #SRAM_OFFSET0 @ build vect addr 152 mov r3, #SRAM_OFFSET1 153 add r1, r1, r3 154 mov r3, #SRAM_OFFSET2 155 add r1, r1, r3 156next: 157 ldmia r0!, {r3 - r10} @ copy from source address [r0] 158 stmia r1!, {r3 - r10} @ copy to target address [r1] 159 cmp r0, r2 @ until source end address [r2] 160 bne next @ loop until equal */ 161#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) 162 /* No need to copy/exec the clock code - DPLL adjust already done 163 * in NAND/oneNAND Boot. 164 */ 165 bl cpy_clk_code @ put dpll adjust code behind vectors 166#endif /* NAND Boot */ 167#endif 168 /* the mask ROM code should have PLL and others stable */ 169#ifndef CONFIG_SKIP_LOWLEVEL_INIT 170 bl cpu_init_crit 171#endif 172 173/* Set stackpointer in internal RAM to call board_init_f */ 174call_board_init_f: 175 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 176 ldr r0,=0x00000000 177 bl board_init_f 178 179/*------------------------------------------------------------------------------*/ 180 181/* 182 * void relocate_code (addr_sp, gd, addr_moni) 183 * 184 * This "function" does not return, instead it continues in RAM 185 * after relocating the monitor code. 186 * 187 */ 188 .globl relocate_code 189relocate_code: 190 mov r4, r0 /* save addr_sp */ 191 mov r5, r1 /* save addr of gd */ 192 mov r6, r2 /* save addr of destination */ 193 mov r7, r2 /* save addr of destination */ 194 195 /* Set up the stack */ 196stack_setup: 197 mov sp, r4 198 199#ifndef CONFIG_SKIP_RELOCATE_UBOOT 200 adr r0, _start 201 ldr r2, _TEXT_BASE 202 ldr r3, _bss_start_ofs 203 add r2, r0, r3 /* r2 <- source end address */ 204 cmp r0, r6 205#ifndef CONFIG_PRELOADER 206 beq jump_2_ram 207#endif 208 209copy_loop: 210 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 211 stmia r6!, {r9-r10} /* copy to target address [r1] */ 212 cmp r0, r2 /* until source end address [r2] */ 213 blo copy_loop 214 215#ifndef CONFIG_PRELOADER 216 /* 217 * fix .rel.dyn relocations 218 */ 219 ldr r0, _TEXT_BASE /* r0 <- Text base */ 220 sub r9, r7, r0 /* r9 <- relocation offset */ 221 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 222 add r10, r10, r0 /* r10 <- sym table in FLASH */ 223 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 224 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 225 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 226 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 227fixloop: 228 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 229 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 230 ldr r1, [r2, #4] 231 and r8, r1, #0xff 232 cmp r8, #23 /* relative fixup? */ 233 beq fixrel 234 cmp r8, #2 /* absolute fixup? */ 235 beq fixabs 236 /* ignore unknown type of fixup */ 237 b fixnext 238fixabs: 239 /* absolute fix: set location to (offset) symbol value */ 240 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 241 add r1, r10, r1 /* r1 <- address of symbol in table */ 242 ldr r1, [r1, #4] /* r1 <- symbol value */ 243 add r1, r9 /* r1 <- relocated sym addr */ 244 b fixnext 245fixrel: 246 /* relative fix: increase location by offset */ 247 ldr r1, [r0] 248 add r1, r1, r9 249fixnext: 250 str r1, [r0] 251 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 252 cmp r2, r3 253 blo fixloop 254 255clear_bss: 256 ldr r0, _bss_start_ofs 257 ldr r1, _bss_end_ofs 258 ldr r3, _TEXT_BASE /* Text base */ 259 mov r4, r7 /* reloc addr */ 260 add r0, r0, r4 261 add r1, r1, r4 262 mov r2, #0x00000000 /* clear */ 263 264clbss_l:str r2, [r0] /* clear loop... */ 265 add r0, r0, #4 266 cmp r0, r1 267 bne clbss_l 268#endif /* #ifndef CONFIG_PRELOADER */ 269#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ 270 271/* 272 * We are done. Do not return, instead branch to second part of board 273 * initialization, now running from RAM. 274 */ 275jump_2_ram: 276 ldr r0, _board_init_r_ofs 277 adr r1, _start 278 add r0, r0, r1 279 add lr, r0, r9 280 /* setup parameters for board_init_r */ 281 mov r0, r5 /* gd_t */ 282 mov r1, r7 /* dest_addr */ 283 /* jump to it ... */ 284 mov pc, lr 285 286_board_init_r_ofs: 287 .word board_init_r - _start 288 289_rel_dyn_start_ofs: 290 .word __rel_dyn_start - _start 291_rel_dyn_end_ofs: 292 .word __rel_dyn_end - _start 293_dynsym_start_ofs: 294 .word __dynsym_start - _start 295 296#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ 297/* 298 * the actual reset code 299 */ 300 301reset: 302 /* 303 * set the cpu to SVC32 mode 304 */ 305 mrs r0, cpsr 306 bic r0, r0, #0x1f 307 orr r0, r0, #0xd3 308 msr cpsr,r0 309 310#if (CONFIG_OMAP34XX) 311 /* Copy vectors to mask ROM indirect addr */ 312 adr r0, _start @ r0 <- current position of code 313 add r0, r0, #4 @ skip reset vector 314 mov r2, #64 @ r2 <- size to copy 315 add r2, r0, r2 @ r2 <- source end address 316 mov r1, #SRAM_OFFSET0 @ build vect addr 317 mov r3, #SRAM_OFFSET1 318 add r1, r1, r3 319 mov r3, #SRAM_OFFSET2 320 add r1, r1, r3 321next: 322 ldmia r0!, {r3 - r10} @ copy from source address [r0] 323 stmia r1!, {r3 - r10} @ copy to target address [r1] 324 cmp r0, r2 @ until source end address [r2] 325 bne next @ loop until equal */ 326#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) 327 /* No need to copy/exec the clock code - DPLL adjust already done 328 * in NAND/oneNAND Boot. 329 */ 330 bl cpy_clk_code @ put dpll adjust code behind vectors 331#endif /* NAND Boot */ 332#endif 333 /* the mask ROM code should have PLL and others stable */ 334#ifndef CONFIG_SKIP_LOWLEVEL_INIT 335 bl cpu_init_crit 336#endif 337 338#ifndef CONFIG_SKIP_RELOCATE_UBOOT 339relocate: @ relocate U-Boot to RAM 340 adr r0, _start @ r0 <- current position of code 341 ldr r1, _TEXT_BASE @ test if we run from flash or RAM 342 cmp r0, r1 @ don't reloc during debug 343 beq stack_setup 344 345 ldr r2, _armboot_start 346 ldr r3, _bss_start 347 sub r2, r3, r2 @ r2 <- size of armboot 348 add r2, r0, r2 @ r2 <- source end address 349 350copy_loop: @ copy 32 bytes at a time 351 ldmia r0!, {r3 - r10} @ copy from source address [r0] 352 stmia r1!, {r3 - r10} @ copy to target address [r1] 353 cmp r0, r2 @ until source end address [r2] 354 blo copy_loop 355#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ 356 357 /* Set up the stack */ 358stack_setup: 359 ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot 360 sub r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area 361 sub r0, r0, #GENERATED_GBL_DATA_SIZE @ bdinfo 362#ifdef CONFIG_USE_IRQ 363 sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ) 364#endif 365 sub sp, r0, #12 @ leave 3 words for abort-stack 366 bic sp, sp, #7 @ 8-byte alignment for ABI compliance 367 368 /* Clear BSS (if any). Is below tx (watch load addr - need space) */ 369clear_bss: 370 ldr r0, _bss_start @ find start of bss segment 371 ldr r1, _bss_end @ stop here 372 mov r2, #0x00000000 @ clear value 373clbss_l: 374 str r2, [r0] @ clear BSS location 375 cmp r0, r1 @ are we at the end yet 376 add r0, r0, #4 @ increment clear index pointer 377 bne clbss_l @ keep clearing till at end 378 379 ldr pc, _start_armboot @ jump to C code 380 381_start_armboot: .word start_armboot 382#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ 383 384/************************************************************************* 385 * 386 * CPU_init_critical registers 387 * 388 * setup important registers 389 * setup memory timing 390 * 391 *************************************************************************/ 392cpu_init_crit: 393 /* 394 * Invalidate L1 I/D 395 */ 396 mov r0, #0 @ set up for MCR 397 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 398 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 399 400 /* 401 * disable MMU stuff and caches 402 */ 403 mrc p15, 0, r0, c1, c0, 0 404 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 405 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 406 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 407 orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB 408 mcr p15, 0, r0, c1, c0, 0 409 410 /* 411 * Jump to board specific initialization... 412 * The Mask ROM will have already initialized 413 * basic memory. Go here to bump up clock rate and handle 414 * wake up conditions. 415 */ 416 mov ip, lr @ persevere link reg across call 417 bl lowlevel_init @ go setup pll,mux,memory 418 mov lr, ip @ restore link 419 mov pc, lr @ back to my caller 420/* 421 ************************************************************************* 422 * 423 * Interrupt handling 424 * 425 ************************************************************************* 426 */ 427@ 428@ IRQ stack frame. 429@ 430#define S_FRAME_SIZE 72 431 432#define S_OLD_R0 68 433#define S_PSR 64 434#define S_PC 60 435#define S_LR 56 436#define S_SP 52 437 438#define S_IP 48 439#define S_FP 44 440#define S_R10 40 441#define S_R9 36 442#define S_R8 32 443#define S_R7 28 444#define S_R6 24 445#define S_R5 20 446#define S_R4 16 447#define S_R3 12 448#define S_R2 8 449#define S_R1 4 450#define S_R0 0 451 452#define MODE_SVC 0x13 453#define I_BIT 0x80 454 455/* 456 * use bad_save_user_regs for abort/prefetch/undef/swi ... 457 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 458 */ 459 460 .macro bad_save_user_regs 461 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current 462 @ user stack 463 stmia sp, {r0 - r12} @ Save user registers (now in 464 @ svc mode) r0-r12 465#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 466 ldr r2, _armboot_start 467 sub r2, r2, #(CONFIG_SYS_MALLOC_LEN) 468 sub r2, r2, #(GENERATED_GBL_DATA_SIZE + 8) @ set base 2 words into abort 469#else 470 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort 471 @ stack 472#endif 473 ldmia r2, {r2 - r3} @ get values for "aborted" pc 474 @ and cpsr (into parm regs) 475 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 476 477 add r5, sp, #S_SP 478 mov r1, lr 479 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 480 mov r0, sp @ save current stack into r0 481 @ (param register) 482 .endm 483 484 .macro irq_save_user_regs 485 sub sp, sp, #S_FRAME_SIZE 486 stmia sp, {r0 - r12} @ Calling r0-r12 487 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! 488 @ a reserved stack spot would 489 @ be good. 490 stmdb r8, {sp, lr}^ @ Calling SP, LR 491 str lr, [r8, #0] @ Save calling PC 492 mrs r6, spsr 493 str r6, [r8, #4] @ Save CPSR 494 str r0, [r8, #8] @ Save OLD_R0 495 mov r0, sp 496 .endm 497 498 .macro irq_restore_user_regs 499 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 500 mov r0, r0 501 ldr lr, [sp, #S_PC] @ Get PC 502 add sp, sp, #S_FRAME_SIZE 503 subs pc, lr, #4 @ return & move spsr_svc into 504 @ cpsr 505 .endm 506 507 .macro get_bad_stack 508#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 509 ldr r13, _armboot_start @ setup our mode stack (enter 510 sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool 511 sub r13, r13, #(GENERATED_GBL_DATA_SIZE + 8) @ move to reserved a couple 512#else 513 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter 514 @ in banked mode) 515#endif 516 517 str lr, [r13] @ save caller lr in position 0 518 @ of saved stack 519 mrs lr, spsr @ get the spsr 520 str lr, [r13, #4] @ save spsr in position 1 of 521 @ saved stack 522 523 mov r13, #MODE_SVC @ prepare SVC-Mode 524 @ msr spsr_c, r13 525 msr spsr, r13 @ switch modes, make sure 526 @ moves will execute 527 mov lr, pc @ capture return pc 528 movs pc, lr @ jump to next instruction & 529 @ switch modes. 530 .endm 531 532 .macro get_bad_stack_swi 533 sub r13, r13, #4 @ space on current stack for 534 @ scratch reg. 535 str r0, [r13] @ save R0's value. 536#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) 537 ldr r0, _armboot_start @ get data regions start 538 sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool 539 sub r0, r0, #(GENERATED_GBL_DATA_SIZE + 8) @ move past gbl and a couple 540#else 541 ldr r0, IRQ_STACK_START_IN @ get data regions start 542 @ spots for abort stack 543#endif 544 str lr, [r0] @ save caller lr in position 0 545 @ of saved stack 546 mrs r0, spsr @ get the spsr 547 str lr, [r0, #4] @ save spsr in position 1 of 548 @ saved stack 549 ldr r0, [r13] @ restore r0 550 add r13, r13, #4 @ pop stack entry 551 .endm 552 553 .macro get_irq_stack @ setup IRQ stack 554 ldr sp, IRQ_STACK_START 555 .endm 556 557 .macro get_fiq_stack @ setup FIQ stack 558 ldr sp, FIQ_STACK_START 559 .endm 560 561/* 562 * exception handlers 563 */ 564 .align 5 565undefined_instruction: 566 get_bad_stack 567 bad_save_user_regs 568 bl do_undefined_instruction 569 570 .align 5 571software_interrupt: 572 get_bad_stack_swi 573 bad_save_user_regs 574 bl do_software_interrupt 575 576 .align 5 577prefetch_abort: 578 get_bad_stack 579 bad_save_user_regs 580 bl do_prefetch_abort 581 582 .align 5 583data_abort: 584 get_bad_stack 585 bad_save_user_regs 586 bl do_data_abort 587 588 .align 5 589not_used: 590 get_bad_stack 591 bad_save_user_regs 592 bl do_not_used 593 594#ifdef CONFIG_USE_IRQ 595 596 .align 5 597irq: 598 get_irq_stack 599 irq_save_user_regs 600 bl do_irq 601 irq_restore_user_regs 602 603 .align 5 604fiq: 605 get_fiq_stack 606 /* someone ought to write a more effective fiq_save_user_regs */ 607 irq_save_user_regs 608 bl do_fiq 609 irq_restore_user_regs 610 611#else 612 613 .align 5 614irq: 615 get_bad_stack 616 bad_save_user_regs 617 bl do_irq 618 619 .align 5 620fiq: 621 get_bad_stack 622 bad_save_user_regs 623 bl do_fiq 624 625#endif 626