1/* 2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com> 12 * 13 * See file CREDITS for list of people who contributed to this 14 * project. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 */ 31 32#include <asm-offsets.h> 33#include <config.h> 34#include <version.h> 35#include <asm/system.h> 36 37.globl _start 38_start: b reset 39 ldr pc, _undefined_instruction 40 ldr pc, _software_interrupt 41 ldr pc, _prefetch_abort 42 ldr pc, _data_abort 43 ldr pc, _not_used 44 ldr pc, _irq 45 ldr pc, _fiq 46#ifdef CONFIG_SPL_BUILD 47_undefined_instruction: .word _undefined_instruction 48_software_interrupt: .word _software_interrupt 49_prefetch_abort: .word _prefetch_abort 50_data_abort: .word _data_abort 51_not_used: .word _not_used 52_irq: .word _irq 53_fiq: .word _fiq 54_pad: .word 0x12345678 /* now 16*4=64 */ 55#else 56_undefined_instruction: .word undefined_instruction 57_software_interrupt: .word software_interrupt 58_prefetch_abort: .word prefetch_abort 59_data_abort: .word data_abort 60_not_used: .word not_used 61_irq: .word irq 62_fiq: .word fiq 63_pad: .word 0x12345678 /* now 16*4=64 */ 64#endif /* CONFIG_SPL_BUILD */ 65 66.global _end_vect 67_end_vect: 68 69 .balignl 16,0xdeadbeef 70/************************************************************************* 71 * 72 * Startup Code (reset vector) 73 * 74 * do important init only if we don't start from memory! 75 * setup Memory and board specific bits prior to relocation. 76 * relocate armboot to ram 77 * setup stack 78 * 79 *************************************************************************/ 80 81.globl _TEXT_BASE 82_TEXT_BASE: 83 .word CONFIG_SYS_TEXT_BASE 84 85/* 86 * These are defined in the board-specific linker script. 87 */ 88.globl _bss_start_ofs 89_bss_start_ofs: 90 .word __bss_start - _start 91 92.global _image_copy_end_ofs 93_image_copy_end_ofs: 94 .word __image_copy_end - _start 95 96.globl _bss_end_ofs 97_bss_end_ofs: 98 .word __bss_end__ - _start 99 100.globl _end_ofs 101_end_ofs: 102 .word _end - _start 103 104#ifdef CONFIG_USE_IRQ 105/* IRQ stack memory (calculated at run-time) */ 106.globl IRQ_STACK_START 107IRQ_STACK_START: 108 .word 0x0badc0de 109 110/* IRQ stack memory (calculated at run-time) */ 111.globl FIQ_STACK_START 112FIQ_STACK_START: 113 .word 0x0badc0de 114#endif 115 116/* IRQ stack memory (calculated at run-time) + 8 bytes */ 117.globl IRQ_STACK_START_IN 118IRQ_STACK_START_IN: 119 .word 0x0badc0de 120 121/* 122 * the actual reset code 123 */ 124 125reset: 126 bl save_boot_params 127 /* 128 * set the cpu to SVC32 mode 129 */ 130 mrs r0, cpsr 131 bic r0, r0, #0x1f 132 orr r0, r0, #0xd3 133 msr cpsr,r0 134 135/* 136 * Setup vector: 137 * (OMAP4 spl TEXT_BASE is not 32 byte aligned. 138 * Continue to use ROM code vector only in OMAP4 spl) 139 */ 140#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) 141 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */ 142 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register 143 bic r0, #CR_V @ V = 0 144 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register 145 146 /* Set vector address in CP15 VBAR register */ 147 ldr r0, =_start 148 mcr p15, 0, r0, c12, c0, 0 @Set VBAR 149#endif 150 151 /* the mask ROM code should have PLL and others stable */ 152#ifndef CONFIG_SKIP_LOWLEVEL_INIT 153 bl cpu_init_cp15 154 bl cpu_init_crit 155#endif 156 157/* Set stackpointer in internal RAM to call board_init_f */ 158call_board_init_f: 159 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 160 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 161 ldr r0,=0x00000000 162 bl board_init_f 163 164/*------------------------------------------------------------------------------*/ 165 166/* 167 * void relocate_code (addr_sp, gd, addr_moni) 168 * 169 * This "function" does not return, instead it continues in RAM 170 * after relocating the monitor code. 171 * 172 */ 173 .globl relocate_code 174relocate_code: 175 mov r4, r0 /* save addr_sp */ 176 mov r5, r1 /* save addr of gd */ 177 mov r6, r2 /* save addr of destination */ 178 179 /* Set up the stack */ 180stack_setup: 181 mov sp, r4 182 183 adr r0, _start 184 cmp r0, r6 185 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 186 beq clear_bss /* skip relocation */ 187 mov r1, r6 /* r1 <- scratch for copy_loop */ 188 ldr r3, _image_copy_end_ofs 189 add r2, r0, r3 /* r2 <- source end address */ 190 191copy_loop: 192 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 193 stmia r1!, {r9-r10} /* copy to target address [r1] */ 194 cmp r0, r2 /* until source end address [r2] */ 195 blo copy_loop 196 197#ifndef CONFIG_SPL_BUILD 198 /* 199 * fix .rel.dyn relocations 200 */ 201 ldr r0, _TEXT_BASE /* r0 <- Text base */ 202 sub r9, r6, r0 /* r9 <- relocation offset */ 203 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 204 add r10, r10, r0 /* r10 <- sym table in FLASH */ 205 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 206 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 207 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 208 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 209fixloop: 210 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 211 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 212 ldr r1, [r2, #4] 213 and r7, r1, #0xff 214 cmp r7, #23 /* relative fixup? */ 215 beq fixrel 216 cmp r7, #2 /* absolute fixup? */ 217 beq fixabs 218 /* ignore unknown type of fixup */ 219 b fixnext 220fixabs: 221 /* absolute fix: set location to (offset) symbol value */ 222 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 223 add r1, r10, r1 /* r1 <- address of symbol in table */ 224 ldr r1, [r1, #4] /* r1 <- symbol value */ 225 add r1, r1, r9 /* r1 <- relocated sym addr */ 226 b fixnext 227fixrel: 228 /* relative fix: increase location by offset */ 229 ldr r1, [r0] 230 add r1, r1, r9 231fixnext: 232 str r1, [r0] 233 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 234 cmp r2, r3 235 blo fixloop 236 b clear_bss 237_rel_dyn_start_ofs: 238 .word __rel_dyn_start - _start 239_rel_dyn_end_ofs: 240 .word __rel_dyn_end - _start 241_dynsym_start_ofs: 242 .word __dynsym_start - _start 243 244#endif /* #ifndef CONFIG_SPL_BUILD */ 245 246clear_bss: 247#ifdef CONFIG_SPL_BUILD 248 /* No relocation for SPL */ 249 ldr r0, =__bss_start 250 ldr r1, =__bss_end__ 251#else 252 ldr r0, _bss_start_ofs 253 ldr r1, _bss_end_ofs 254 mov r4, r6 /* reloc addr */ 255 add r0, r0, r4 256 add r1, r1, r4 257#endif 258 mov r2, #0x00000000 /* clear */ 259 260clbss_l:str r2, [r0] /* clear loop... */ 261 add r0, r0, #4 262 cmp r0, r1 263 bne clbss_l 264 265/* 266 * We are done. Do not return, instead branch to second part of board 267 * initialization, now running from RAM. 268 */ 269jump_2_ram: 270/* 271 * If I-cache is enabled invalidate it 272 */ 273#ifndef CONFIG_SYS_ICACHE_OFF 274 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 275 mcr p15, 0, r0, c7, c10, 4 @ DSB 276 mcr p15, 0, r0, c7, c5, 4 @ ISB 277#endif 278 ldr r0, _board_init_r_ofs 279 adr r1, _start 280 add lr, r0, r1 281 add lr, lr, r9 282 /* setup parameters for board_init_r */ 283 mov r0, r5 /* gd_t */ 284 mov r1, r6 /* dest_addr */ 285 /* jump to it ... */ 286 mov pc, lr 287 288_board_init_r_ofs: 289 .word board_init_r - _start 290 291/************************************************************************* 292 * 293 * cpu_init_cp15 294 * 295 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless 296 * CONFIG_SYS_ICACHE_OFF is defined. 297 * 298 *************************************************************************/ 299.globl cpu_init_cp15 300cpu_init_cp15: 301 /* 302 * Invalidate L1 I/D 303 */ 304 mov r0, #0 @ set up for MCR 305 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 306 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 307 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array 308 mcr p15, 0, r0, c7, c10, 4 @ DSB 309 mcr p15, 0, r0, c7, c5, 4 @ ISB 310 311 /* 312 * disable MMU stuff and caches 313 */ 314 mrc p15, 0, r0, c1, c0, 0 315 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 316 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 317 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 318 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB 319#ifdef CONFIG_SYS_ICACHE_OFF 320 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache 321#else 322 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache 323#endif 324 mcr p15, 0, r0, c1, c0, 0 325 mov pc, lr @ back to my caller 326 327 328#ifndef CONFIG_SKIP_LOWLEVEL_INIT 329/************************************************************************* 330 * 331 * CPU_init_critical registers 332 * 333 * setup important registers 334 * setup memory timing 335 * 336 *************************************************************************/ 337cpu_init_crit: 338 /* 339 * Jump to board specific initialization... 340 * The Mask ROM will have already initialized 341 * basic memory. Go here to bump up clock rate and handle 342 * wake up conditions. 343 */ 344 mov ip, lr @ persevere link reg across call 345 bl lowlevel_init @ go setup pll,mux,memory 346 mov lr, ip @ restore link 347 mov pc, lr @ back to my caller 348#endif 349 350#ifndef CONFIG_SPL_BUILD 351/* 352 ************************************************************************* 353 * 354 * Interrupt handling 355 * 356 ************************************************************************* 357 */ 358@ 359@ IRQ stack frame. 360@ 361#define S_FRAME_SIZE 72 362 363#define S_OLD_R0 68 364#define S_PSR 64 365#define S_PC 60 366#define S_LR 56 367#define S_SP 52 368 369#define S_IP 48 370#define S_FP 44 371#define S_R10 40 372#define S_R9 36 373#define S_R8 32 374#define S_R7 28 375#define S_R6 24 376#define S_R5 20 377#define S_R4 16 378#define S_R3 12 379#define S_R2 8 380#define S_R1 4 381#define S_R0 0 382 383#define MODE_SVC 0x13 384#define I_BIT 0x80 385 386/* 387 * use bad_save_user_regs for abort/prefetch/undef/swi ... 388 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 389 */ 390 391 .macro bad_save_user_regs 392 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current 393 @ user stack 394 stmia sp, {r0 - r12} @ Save user registers (now in 395 @ svc mode) r0-r12 396 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort 397 @ stack 398 ldmia r2, {r2 - r3} @ get values for "aborted" pc 399 @ and cpsr (into parm regs) 400 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 401 402 add r5, sp, #S_SP 403 mov r1, lr 404 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 405 mov r0, sp @ save current stack into r0 406 @ (param register) 407 .endm 408 409 .macro irq_save_user_regs 410 sub sp, sp, #S_FRAME_SIZE 411 stmia sp, {r0 - r12} @ Calling r0-r12 412 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! 413 @ a reserved stack spot would 414 @ be good. 415 stmdb r8, {sp, lr}^ @ Calling SP, LR 416 str lr, [r8, #0] @ Save calling PC 417 mrs r6, spsr 418 str r6, [r8, #4] @ Save CPSR 419 str r0, [r8, #8] @ Save OLD_R0 420 mov r0, sp 421 .endm 422 423 .macro irq_restore_user_regs 424 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 425 mov r0, r0 426 ldr lr, [sp, #S_PC] @ Get PC 427 add sp, sp, #S_FRAME_SIZE 428 subs pc, lr, #4 @ return & move spsr_svc into 429 @ cpsr 430 .endm 431 432 .macro get_bad_stack 433 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter 434 @ in banked mode) 435 436 str lr, [r13] @ save caller lr in position 0 437 @ of saved stack 438 mrs lr, spsr @ get the spsr 439 str lr, [r13, #4] @ save spsr in position 1 of 440 @ saved stack 441 442 mov r13, #MODE_SVC @ prepare SVC-Mode 443 @ msr spsr_c, r13 444 msr spsr, r13 @ switch modes, make sure 445 @ moves will execute 446 mov lr, pc @ capture return pc 447 movs pc, lr @ jump to next instruction & 448 @ switch modes. 449 .endm 450 451 .macro get_bad_stack_swi 452 sub r13, r13, #4 @ space on current stack for 453 @ scratch reg. 454 str r0, [r13] @ save R0's value. 455 ldr r0, IRQ_STACK_START_IN @ get data regions start 456 @ spots for abort stack 457 str lr, [r0] @ save caller lr in position 0 458 @ of saved stack 459 mrs r0, spsr @ get the spsr 460 str lr, [r0, #4] @ save spsr in position 1 of 461 @ saved stack 462 ldr r0, [r13] @ restore r0 463 add r13, r13, #4 @ pop stack entry 464 .endm 465 466 .macro get_irq_stack @ setup IRQ stack 467 ldr sp, IRQ_STACK_START 468 .endm 469 470 .macro get_fiq_stack @ setup FIQ stack 471 ldr sp, FIQ_STACK_START 472 .endm 473 474/* 475 * exception handlers 476 */ 477 .align 5 478undefined_instruction: 479 get_bad_stack 480 bad_save_user_regs 481 bl do_undefined_instruction 482 483 .align 5 484software_interrupt: 485 get_bad_stack_swi 486 bad_save_user_regs 487 bl do_software_interrupt 488 489 .align 5 490prefetch_abort: 491 get_bad_stack 492 bad_save_user_regs 493 bl do_prefetch_abort 494 495 .align 5 496data_abort: 497 get_bad_stack 498 bad_save_user_regs 499 bl do_data_abort 500 501 .align 5 502not_used: 503 get_bad_stack 504 bad_save_user_regs 505 bl do_not_used 506 507#ifdef CONFIG_USE_IRQ 508 509 .align 5 510irq: 511 get_irq_stack 512 irq_save_user_regs 513 bl do_irq 514 irq_restore_user_regs 515 516 .align 5 517fiq: 518 get_fiq_stack 519 /* someone ought to write a more effective fiq_save_user_regs */ 520 irq_save_user_regs 521 bl do_fiq 522 irq_restore_user_regs 523 524#else 525 526 .align 5 527irq: 528 get_bad_stack 529 bad_save_user_regs 530 bl do_irq 531 532 .align 5 533fiq: 534 get_bad_stack 535 bad_save_user_regs 536 bl do_fiq 537 538#endif /* CONFIG_USE_IRQ */ 539#endif /* CONFIG_SPL_BUILD */ 540