xref: /openbmc/u-boot/arch/arm/cpu/armv7/start.S (revision 00f792e0) 
1/*
2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
3 *
4 * Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
5 *
6 * Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003	Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 */
31
32#include <asm-offsets.h>
33#include <config.h>
34#include <version.h>
35#include <asm/system.h>
36#include <linux/linkage.h>
37
38.globl _start
39_start: b	reset
40	ldr	pc, _undefined_instruction
41	ldr	pc, _software_interrupt
42	ldr	pc, _prefetch_abort
43	ldr	pc, _data_abort
44	ldr	pc, _not_used
45	ldr	pc, _irq
46	ldr	pc, _fiq
47#ifdef CONFIG_SPL_BUILD
48_undefined_instruction: .word _undefined_instruction
49_software_interrupt:	.word _software_interrupt
50_prefetch_abort:	.word _prefetch_abort
51_data_abort:		.word _data_abort
52_not_used:		.word _not_used
53_irq:			.word _irq
54_fiq:			.word _fiq
55_pad:			.word 0x12345678 /* now 16*4=64 */
56#else
57_undefined_instruction: .word undefined_instruction
58_software_interrupt:	.word software_interrupt
59_prefetch_abort:	.word prefetch_abort
60_data_abort:		.word data_abort
61_not_used:		.word not_used
62_irq:			.word irq
63_fiq:			.word fiq
64_pad:			.word 0x12345678 /* now 16*4=64 */
65#endif	/* CONFIG_SPL_BUILD */
66
67.global _end_vect
68_end_vect:
69
70	.balignl 16,0xdeadbeef
71/*************************************************************************
72 *
73 * Startup Code (reset vector)
74 *
75 * do important init only if we don't start from memory!
76 * setup Memory and board specific bits prior to relocation.
77 * relocate armboot to ram
78 * setup stack
79 *
80 *************************************************************************/
81
82.globl _TEXT_BASE
83_TEXT_BASE:
84#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
85	.word	CONFIG_SPL_TEXT_BASE
86#else
87	.word	CONFIG_SYS_TEXT_BASE
88#endif
89
90/*
91 * These are defined in the board-specific linker script.
92 */
93.globl _bss_start_ofs
94_bss_start_ofs:
95	.word __bss_start - _start
96
97.globl _bss_end_ofs
98_bss_end_ofs:
99	.word __bss_end - _start
100
101.globl _end_ofs
102_end_ofs:
103	.word _end - _start
104
105#ifdef CONFIG_USE_IRQ
106/* IRQ stack memory (calculated at run-time) */
107.globl IRQ_STACK_START
108IRQ_STACK_START:
109	.word	0x0badc0de
110
111/* IRQ stack memory (calculated at run-time) */
112.globl FIQ_STACK_START
113FIQ_STACK_START:
114	.word 0x0badc0de
115#endif
116
117/* IRQ stack memory (calculated at run-time) + 8 bytes */
118.globl IRQ_STACK_START_IN
119IRQ_STACK_START_IN:
120	.word	0x0badc0de
121
122/*
123 * the actual reset code
124 */
125
126reset:
127	bl	save_boot_params
128	/*
129	 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
130	 * except if in HYP mode already
131	 */
132	mrs	r0, cpsr
133	and	r1, r0, #0x1f		@ mask mode bits
134	teq	r1, #0x1a		@ test for HYP mode
135	bicne	r0, r0, #0x1f		@ clear all mode bits
136	orrne	r0, r0, #0x13		@ set SVC mode
137	orr	r0, r0, #0xc0		@ disable FIQ and IRQ
138	msr	cpsr,r0
139
140/*
141 * Setup vector:
142 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
143 * Continue to use ROM code vector only in OMAP4 spl)
144 */
145#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
146	/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
147	mrc	p15, 0, r0, c1, c0, 0	@ Read CP15 SCTRL Register
148	bic	r0, #CR_V		@ V = 0
149	mcr	p15, 0, r0, c1, c0, 0	@ Write CP15 SCTRL Register
150
151	/* Set vector address in CP15 VBAR register */
152	ldr	r0, =_start
153	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
154#endif
155
156	/* the mask ROM code should have PLL and others stable */
157#ifndef CONFIG_SKIP_LOWLEVEL_INIT
158	bl	cpu_init_cp15
159	bl	cpu_init_crit
160#endif
161
162	bl	_main
163
164/*------------------------------------------------------------------------------*/
165
166ENTRY(c_runtime_cpu_setup)
167/*
168 * If I-cache is enabled invalidate it
169 */
170#ifndef CONFIG_SYS_ICACHE_OFF
171	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
172	mcr     p15, 0, r0, c7, c10, 4	@ DSB
173	mcr     p15, 0, r0, c7, c5, 4	@ ISB
174#endif
175/*
176 * Move vector table
177 */
178	/* Set vector address in CP15 VBAR register */
179	ldr     r0, =_start
180	mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
181
182	bx	lr
183
184ENDPROC(c_runtime_cpu_setup)
185
186/*************************************************************************
187 *
188 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
189 *	__attribute__((weak));
190 *
191 * Stack pointer is not yet initialized at this moment
192 * Don't save anything to stack even if compiled with -O0
193 *
194 *************************************************************************/
195ENTRY(save_boot_params)
196	bx	lr			@ back to my caller
197ENDPROC(save_boot_params)
198	.weak	save_boot_params
199
200/*************************************************************************
201 *
202 * cpu_init_cp15
203 *
204 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
205 * CONFIG_SYS_ICACHE_OFF is defined.
206 *
207 *************************************************************************/
208ENTRY(cpu_init_cp15)
209	/*
210	 * Invalidate L1 I/D
211	 */
212	mov	r0, #0			@ set up for MCR
213	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
214	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
215	mcr	p15, 0, r0, c7, c5, 6	@ invalidate BP array
216	mcr     p15, 0, r0, c7, c10, 4	@ DSB
217	mcr     p15, 0, r0, c7, c5, 4	@ ISB
218
219	/*
220	 * disable MMU stuff and caches
221	 */
222	mrc	p15, 0, r0, c1, c0, 0
223	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
224	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
225	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
226	orr	r0, r0, #0x00000800	@ set bit 11 (Z---) BTB
227#ifdef CONFIG_SYS_ICACHE_OFF
228	bic	r0, r0, #0x00001000	@ clear bit 12 (I) I-cache
229#else
230	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-cache
231#endif
232	mcr	p15, 0, r0, c1, c0, 0
233
234#ifdef CONFIG_ARM_ERRATA_716044
235	mrc	p15, 0, r0, c1, c0, 0	@ read system control register
236	orr	r0, r0, #1 << 11	@ set bit #11
237	mcr	p15, 0, r0, c1, c0, 0	@ write system control register
238#endif
239
240#ifdef CONFIG_ARM_ERRATA_742230
241	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
242	orr	r0, r0, #1 << 4		@ set bit #4
243	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
244#endif
245
246#ifdef CONFIG_ARM_ERRATA_743622
247	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
248	orr	r0, r0, #1 << 6		@ set bit #6
249	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
250#endif
251
252#ifdef CONFIG_ARM_ERRATA_751472
253	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
254	orr	r0, r0, #1 << 11	@ set bit #11
255	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
256#endif
257
258	mov	pc, lr			@ back to my caller
259ENDPROC(cpu_init_cp15)
260
261#ifndef CONFIG_SKIP_LOWLEVEL_INIT
262/*************************************************************************
263 *
264 * CPU_init_critical registers
265 *
266 * setup important registers
267 * setup memory timing
268 *
269 *************************************************************************/
270ENTRY(cpu_init_crit)
271	/*
272	 * Jump to board specific initialization...
273	 * The Mask ROM will have already initialized
274	 * basic memory. Go here to bump up clock rate and handle
275	 * wake up conditions.
276	 */
277	b	lowlevel_init		@ go setup pll,mux,memory
278ENDPROC(cpu_init_crit)
279#endif
280
281#ifndef CONFIG_SPL_BUILD
282/*
283 *************************************************************************
284 *
285 * Interrupt handling
286 *
287 *************************************************************************
288 */
289@
290@ IRQ stack frame.
291@
292#define S_FRAME_SIZE	72
293
294#define S_OLD_R0	68
295#define S_PSR		64
296#define S_PC		60
297#define S_LR		56
298#define S_SP		52
299
300#define S_IP		48
301#define S_FP		44
302#define S_R10		40
303#define S_R9		36
304#define S_R8		32
305#define S_R7		28
306#define S_R6		24
307#define S_R5		20
308#define S_R4		16
309#define S_R3		12
310#define S_R2		8
311#define S_R1		4
312#define S_R0		0
313
314#define MODE_SVC 0x13
315#define I_BIT	 0x80
316
317/*
318 * use bad_save_user_regs for abort/prefetch/undef/swi ...
319 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
320 */
321
322	.macro	bad_save_user_regs
323	sub	sp, sp, #S_FRAME_SIZE		@ carve out a frame on current
324						@ user stack
325	stmia	sp, {r0 - r12}			@ Save user registers (now in
326						@ svc mode) r0-r12
327	ldr	r2, IRQ_STACK_START_IN		@ set base 2 words into abort
328						@ stack
329	ldmia	r2, {r2 - r3}			@ get values for "aborted" pc
330						@ and cpsr (into parm regs)
331	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
332
333	add	r5, sp, #S_SP
334	mov	r1, lr
335	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
336	mov	r0, sp				@ save current stack into r0
337						@ (param register)
338	.endm
339
340	.macro	irq_save_user_regs
341	sub	sp, sp, #S_FRAME_SIZE
342	stmia	sp, {r0 - r12}			@ Calling r0-r12
343	add	r8, sp, #S_PC			@ !! R8 NEEDS to be saved !!
344						@ a reserved stack spot would
345						@ be good.
346	stmdb	r8, {sp, lr}^			@ Calling SP, LR
347	str	lr, [r8, #0]			@ Save calling PC
348	mrs	r6, spsr
349	str	r6, [r8, #4]			@ Save CPSR
350	str	r0, [r8, #8]			@ Save OLD_R0
351	mov	r0, sp
352	.endm
353
354	.macro	irq_restore_user_regs
355	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
356	mov	r0, r0
357	ldr	lr, [sp, #S_PC]			@ Get PC
358	add	sp, sp, #S_FRAME_SIZE
359	subs	pc, lr, #4			@ return & move spsr_svc into
360						@ cpsr
361	.endm
362
363	.macro get_bad_stack
364	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack (enter
365						@ in banked mode)
366
367	str	lr, [r13]			@ save caller lr in position 0
368						@ of saved stack
369	mrs	lr, spsr			@ get the spsr
370	str	lr, [r13, #4]			@ save spsr in position 1 of
371						@ saved stack
372
373	mov	r13, #MODE_SVC			@ prepare SVC-Mode
374	@ msr	spsr_c, r13
375	msr	spsr, r13			@ switch modes, make sure
376						@ moves will execute
377	mov	lr, pc				@ capture return pc
378	movs	pc, lr				@ jump to next instruction &
379						@ switch modes.
380	.endm
381
382	.macro get_bad_stack_swi
383	sub	r13, r13, #4			@ space on current stack for
384						@ scratch reg.
385	str	r0, [r13]			@ save R0's value.
386	ldr	r0, IRQ_STACK_START_IN		@ get data regions start
387						@ spots for abort stack
388	str	lr, [r0]			@ save caller lr in position 0
389						@ of saved stack
390	mrs	lr, spsr			@ get the spsr
391	str	lr, [r0, #4]			@ save spsr in position 1 of
392						@ saved stack
393	ldr	lr, [r0]			@ restore lr
394	ldr	r0, [r13]			@ restore r0
395	add	r13, r13, #4			@ pop stack entry
396	.endm
397
398	.macro get_irq_stack			@ setup IRQ stack
399	ldr	sp, IRQ_STACK_START
400	.endm
401
402	.macro get_fiq_stack			@ setup FIQ stack
403	ldr	sp, FIQ_STACK_START
404	.endm
405
406/*
407 * exception handlers
408 */
409	.align	5
410undefined_instruction:
411	get_bad_stack
412	bad_save_user_regs
413	bl	do_undefined_instruction
414
415	.align	5
416software_interrupt:
417	get_bad_stack_swi
418	bad_save_user_regs
419	bl	do_software_interrupt
420
421	.align	5
422prefetch_abort:
423	get_bad_stack
424	bad_save_user_regs
425	bl	do_prefetch_abort
426
427	.align	5
428data_abort:
429	get_bad_stack
430	bad_save_user_regs
431	bl	do_data_abort
432
433	.align	5
434not_used:
435	get_bad_stack
436	bad_save_user_regs
437	bl	do_not_used
438
439#ifdef CONFIG_USE_IRQ
440
441	.align	5
442irq:
443	get_irq_stack
444	irq_save_user_regs
445	bl	do_irq
446	irq_restore_user_regs
447
448	.align	5
449fiq:
450	get_fiq_stack
451	/* someone ought to write a more effective fiq_save_user_regs */
452	irq_save_user_regs
453	bl	do_fiq
454	irq_restore_user_regs
455
456#else
457
458	.align	5
459irq:
460	get_bad_stack
461	bad_save_user_regs
462	bl	do_irq
463
464	.align	5
465fiq:
466	get_bad_stack
467	bad_save_user_regs
468	bl	do_fiq
469
470#endif /* CONFIG_USE_IRQ */
471#endif /* CONFIG_SPL_BUILD */
472