1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * 4 * Donghwa Lee <dh09.lee@samsung.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <errno.h> 27 #include <pwm.h> 28 #include <asm/io.h> 29 #include <asm/arch/pwm.h> 30 #include <asm/arch/clk.h> 31 32 int pwm_enable(int pwm_id) 33 { 34 const struct s5p_timer *pwm = 35 (struct s5p_timer *)samsung_get_base_timer(); 36 unsigned long tcon; 37 38 tcon = readl(&pwm->tcon); 39 tcon |= TCON_START(pwm_id); 40 41 writel(tcon, &pwm->tcon); 42 43 return 0; 44 } 45 46 void pwm_disable(int pwm_id) 47 { 48 const struct s5p_timer *pwm = 49 (struct s5p_timer *)samsung_get_base_timer(); 50 unsigned long tcon; 51 52 tcon = readl(&pwm->tcon); 53 tcon &= ~TCON_START(pwm_id); 54 55 writel(tcon, &pwm->tcon); 56 } 57 58 static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq) 59 { 60 unsigned long tin_parent_rate; 61 unsigned int div; 62 63 tin_parent_rate = get_pwm_clk(); 64 65 for (div = 2; div <= 16; div *= 2) { 66 if ((tin_parent_rate / (div << 16)) < freq) 67 return tin_parent_rate / div; 68 } 69 70 return tin_parent_rate / 16; 71 } 72 73 #define NS_IN_HZ (1000000000UL) 74 75 int pwm_config(int pwm_id, int duty_ns, int period_ns) 76 { 77 const struct s5p_timer *pwm = 78 (struct s5p_timer *)samsung_get_base_timer(); 79 unsigned int offset; 80 unsigned long tin_rate; 81 unsigned long tin_ns; 82 unsigned long period; 83 unsigned long tcon; 84 unsigned long tcnt; 85 unsigned long timer_rate_hz; 86 unsigned long tcmp; 87 88 /* 89 * We currently avoid using 64bit arithmetic by using the 90 * fact that anything faster than 1GHz is easily representable 91 * by 32bits. 92 */ 93 if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ) 94 return -ERANGE; 95 96 if (duty_ns > period_ns) 97 return -EINVAL; 98 99 period = NS_IN_HZ / period_ns; 100 101 /* Check to see if we are changing the clock rate of the PWM */ 102 tin_rate = pwm_calc_tin(pwm_id, period); 103 timer_rate_hz = tin_rate; 104 105 tin_ns = NS_IN_HZ / tin_rate; 106 tcnt = period_ns / tin_ns; 107 108 /* Note, counters count down */ 109 tcmp = duty_ns / tin_ns; 110 tcmp = tcnt - tcmp; 111 112 /* 113 * the pwm hw only checks the compare register after a decrement, 114 * so the pin never toggles if tcmp = tcnt 115 */ 116 if (tcmp == tcnt) 117 tcmp--; 118 119 if (tcmp < 0) 120 tcmp = 0; 121 122 /* Update the PWM register block. */ 123 offset = pwm_id * 3; 124 if (pwm_id < 4) { 125 writel(tcnt, &pwm->tcntb0 + offset); 126 writel(tcmp, &pwm->tcmpb0 + offset); 127 } 128 129 tcon = readl(&pwm->tcon); 130 tcon |= TCON_UPDATE(pwm_id); 131 if (pwm_id < 4) 132 tcon |= TCON_AUTO_RELOAD(pwm_id); 133 else 134 tcon |= TCON4_AUTO_RELOAD; 135 writel(tcon, &pwm->tcon); 136 137 tcon &= ~TCON_UPDATE(pwm_id); 138 writel(tcon, &pwm->tcon); 139 140 return 0; 141 } 142 143 int pwm_init(int pwm_id, int div, int invert) 144 { 145 u32 val; 146 const struct s5p_timer *pwm = 147 (struct s5p_timer *)samsung_get_base_timer(); 148 unsigned long timer_rate_hz; 149 unsigned int offset, prescaler; 150 151 /* 152 * Timer Freq(HZ) = 153 * PWM_CLK / { (prescaler_value + 1) * (divider_value) } 154 */ 155 156 val = readl(&pwm->tcfg0); 157 if (pwm_id < 2) { 158 prescaler = PRESCALER_0; 159 val &= ~0xff; 160 val |= (prescaler & 0xff); 161 } else { 162 prescaler = PRESCALER_1; 163 val &= ~(0xff << 8); 164 val |= (prescaler & 0xff) << 8; 165 } 166 writel(val, &pwm->tcfg0); 167 val = readl(&pwm->tcfg1); 168 val &= ~(0xf << MUX_DIV_SHIFT(pwm_id)); 169 val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id); 170 writel(val, &pwm->tcfg1); 171 172 timer_rate_hz = get_pwm_clk() / ((prescaler + 1) * 173 (div + 1)); 174 175 timer_rate_hz = timer_rate_hz / 100; 176 177 /* set count value */ 178 offset = pwm_id * 3; 179 writel(timer_rate_hz, &pwm->tcntb0 + offset); 180 181 val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id)); 182 if (invert && (pwm_id < 4)) 183 val |= TCON_INVERTER(pwm_id); 184 writel(val, &pwm->tcon); 185 186 pwm_enable(pwm_id); 187 188 return 0; 189 } 190