1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * 4 * Donghwa Lee <dh09.lee@samsung.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <errno.h> 27 #include <pwm.h> 28 #include <asm/io.h> 29 #include <asm/arch/pwm.h> 30 #include <asm/arch/clk.h> 31 32 int pwm_enable(int pwm_id) 33 { 34 const struct s5p_timer *pwm = 35 (struct s5p_timer *)samsung_get_base_timer(); 36 unsigned long tcon; 37 38 tcon = readl(&pwm->tcon); 39 tcon |= TCON_START(pwm_id); 40 41 writel(tcon, &pwm->tcon); 42 43 return 0; 44 } 45 46 void pwm_disable(int pwm_id) 47 { 48 const struct s5p_timer *pwm = 49 (struct s5p_timer *)samsung_get_base_timer(); 50 unsigned long tcon; 51 52 tcon = readl(&pwm->tcon); 53 tcon &= ~TCON_START(pwm_id); 54 55 writel(tcon, &pwm->tcon); 56 } 57 58 static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq) 59 { 60 unsigned long tin_parent_rate; 61 unsigned int div; 62 63 tin_parent_rate = get_pwm_clk(); 64 65 for (div = 2; div <= 16; div *= 2) { 66 if ((tin_parent_rate / (div << 16)) < freq) 67 return tin_parent_rate / div; 68 } 69 70 return tin_parent_rate / 16; 71 } 72 73 #define NS_IN_HZ (1000000000UL) 74 75 int pwm_config(int pwm_id, int duty_ns, int period_ns) 76 { 77 const struct s5p_timer *pwm = 78 (struct s5p_timer *)samsung_get_base_timer(); 79 unsigned int offset; 80 unsigned long tin_rate; 81 unsigned long tin_ns; 82 unsigned long period; 83 unsigned long tcon; 84 unsigned long tcnt; 85 unsigned long tcmp; 86 87 /* 88 * We currently avoid using 64bit arithmetic by using the 89 * fact that anything faster than 1GHz is easily representable 90 * by 32bits. 91 */ 92 if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ) 93 return -ERANGE; 94 95 if (duty_ns > period_ns) 96 return -EINVAL; 97 98 period = NS_IN_HZ / period_ns; 99 100 /* Check to see if we are changing the clock rate of the PWM */ 101 tin_rate = pwm_calc_tin(pwm_id, period); 102 103 tin_ns = NS_IN_HZ / tin_rate; 104 tcnt = period_ns / tin_ns; 105 106 /* Note, counters count down */ 107 tcmp = duty_ns / tin_ns; 108 tcmp = tcnt - tcmp; 109 110 /* 111 * the pwm hw only checks the compare register after a decrement, 112 * so the pin never toggles if tcmp = tcnt 113 */ 114 if (tcmp == tcnt) 115 tcmp--; 116 117 if (tcmp < 0) 118 tcmp = 0; 119 120 /* Update the PWM register block. */ 121 offset = pwm_id * 3; 122 if (pwm_id < 4) { 123 writel(tcnt, &pwm->tcntb0 + offset); 124 writel(tcmp, &pwm->tcmpb0 + offset); 125 } 126 127 tcon = readl(&pwm->tcon); 128 tcon |= TCON_UPDATE(pwm_id); 129 if (pwm_id < 4) 130 tcon |= TCON_AUTO_RELOAD(pwm_id); 131 else 132 tcon |= TCON4_AUTO_RELOAD; 133 writel(tcon, &pwm->tcon); 134 135 tcon &= ~TCON_UPDATE(pwm_id); 136 writel(tcon, &pwm->tcon); 137 138 return 0; 139 } 140 141 int pwm_init(int pwm_id, int div, int invert) 142 { 143 u32 val; 144 const struct s5p_timer *pwm = 145 (struct s5p_timer *)samsung_get_base_timer(); 146 unsigned long timer_rate_hz; 147 unsigned int offset, prescaler; 148 149 /* 150 * Timer Freq(HZ) = 151 * PWM_CLK / { (prescaler_value + 1) * (divider_value) } 152 */ 153 154 val = readl(&pwm->tcfg0); 155 if (pwm_id < 2) { 156 prescaler = PRESCALER_0; 157 val &= ~0xff; 158 val |= (prescaler & 0xff); 159 } else { 160 prescaler = PRESCALER_1; 161 val &= ~(0xff << 8); 162 val |= (prescaler & 0xff) << 8; 163 } 164 writel(val, &pwm->tcfg0); 165 val = readl(&pwm->tcfg1); 166 val &= ~(0xf << MUX_DIV_SHIFT(pwm_id)); 167 val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id); 168 writel(val, &pwm->tcfg1); 169 170 timer_rate_hz = get_pwm_clk() / ((prescaler + 1) * 171 (div + 1)); 172 173 timer_rate_hz = timer_rate_hz / CONFIG_SYS_HZ; 174 175 /* set count value */ 176 offset = pwm_id * 3; 177 writel(timer_rate_hz, &pwm->tcntb0 + offset); 178 179 val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id)); 180 if (invert && (pwm_id < 4)) 181 val |= TCON_INVERTER(pwm_id); 182 writel(val, &pwm->tcon); 183 184 pwm_enable(pwm_id); 185 186 return 0; 187 } 188