1/* 2 * code for switching cores into non-secure state and into HYP mode 3 * 4 * Copyright (c) 2013 Andre Przywara <andre.przywara@linaro.org> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#include <config.h> 10#include <linux/linkage.h> 11#include <asm/gic.h> 12#include <asm/armv7.h> 13 14.arch_extension sec 15.arch_extension virt 16 17/* the vector table for secure state and HYP mode */ 18_monitor_vectors: 19 .word 0 /* reset */ 20 .word 0 /* undef */ 21 adr pc, _secure_monitor 22 .word 0 23 .word 0 24 adr pc, _hyp_trap 25 .word 0 26 .word 0 27 28/* 29 * secure monitor handler 30 * U-boot calls this "software interrupt" in start.S 31 * This is executed on a "smc" instruction, we use a "smc #0" to switch 32 * to non-secure state. 33 * We use only r0 and r1 here, due to constraints in the caller. 34 */ 35 .align 5 36_secure_monitor: 37 mrc p15, 0, r1, c1, c1, 0 @ read SCR 38 bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits 39 orr r1, r1, #0x31 @ enable NS, AW, FW bits 40 41#ifdef CONFIG_ARMV7_VIRT 42 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 43 and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits 44 cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT) 45 orreq r1, r1, #0x100 @ allow HVC instruction 46#endif 47 48 mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) 49 50#ifdef CONFIG_ARMV7_VIRT 51 mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value 52 mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR 53#endif 54 55 movs pc, lr @ return to non-secure SVC 56 57_hyp_trap: 58 mrs lr, elr_hyp @ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1 59 mov pc, lr @ do no switch modes, but 60 @ return to caller 61 62/* 63 * Secondary CPUs start here and call the code for the core specific parts 64 * of the non-secure and HYP mode transition. The GIC distributor specific 65 * code has already been executed by a C function before. 66 * Then they go back to wfi and wait to be woken up by the kernel again. 67 */ 68ENTRY(_smp_pen) 69 mrs r0, cpsr 70 orr r0, r0, #0xc0 71 msr cpsr, r0 @ disable interrupts 72 ldr r1, =_start 73 mcr p15, 0, r1, c12, c0, 0 @ set VBAR 74 75 bl _nonsec_init 76 mov r12, r0 @ save GICC address 77#ifdef CONFIG_ARMV7_VIRT 78 bl _switch_to_hyp 79#endif 80 81 ldr r1, [r12, #GICC_IAR] @ acknowledge IPI 82 str r1, [r12, #GICC_EOIR] @ signal end of interrupt 83 84 adr r0, _smp_pen @ do not use this address again 85 b smp_waitloop @ wait for IPIs, board specific 86ENDPROC(_smp_pen) 87 88/* 89 * Switch a core to non-secure state. 90 * 91 * 1. initialize the GIC per-core interface 92 * 2. allow coprocessor access in non-secure modes 93 * 3. switch the cpu mode (by calling "smc #0") 94 * 95 * Called from smp_pen by secondary cores and directly by the BSP. 96 * Do not assume that the stack is available and only use registers 97 * r0-r3 and r12. 98 * 99 * PERIPHBASE is used to get the GIC address. This could be 40 bits long, 100 * though, but we check this in C before calling this function. 101 */ 102ENTRY(_nonsec_init) 103#ifdef CONFIG_ARM_GIC_BASE_ADDRESS 104 ldr r2, =CONFIG_ARM_GIC_BASE_ADDRESS 105#else 106 mrc p15, 4, r2, c15, c0, 0 @ read CBAR 107 bfc r2, #0, #15 @ clear reserved bits 108#endif 109 add r3, r2, #GIC_DIST_OFFSET @ GIC dist i/f offset 110 mvn r1, #0 @ all bits to 1 111 str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts 112 113 mrc p15, 0, r0, c0, c0, 0 @ read MIDR 114 ldr r1, =MIDR_PRIMARY_PART_MASK 115 and r0, r0, r1 @ mask out variant and revision 116 117 ldr r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK 118 cmp r0, r1 @ check for Cortex-A7 119 120 ldr r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK 121 cmpne r0, r1 @ check for Cortex-A15 122 123 movne r1, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9 124 moveq r1, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7 125 add r3, r2, r1 @ r3 = GIC CPU i/f addr 126 127 mov r1, #1 @ set GICC_CTLR[enable] 128 str r1, [r3, #GICC_CTLR] @ and clear all other bits 129 mov r1, #0xff 130 str r1, [r3, #GICC_PMR] @ set priority mask register 131 132 movw r1, #0x3fff 133 movt r1, #0x0006 134 mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec 135 136/* The CNTFRQ register of the generic timer needs to be 137 * programmed in secure state. Some primary bootloaders / firmware 138 * omit this, so if the frequency is provided in the configuration, 139 * we do this here instead. 140 * But first check if we have the generic timer. 141 */ 142#ifdef CONFIG_SYS_CLK_FREQ 143 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 144 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits 145 cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT) 146 ldreq r1, =CONFIG_SYS_CLK_FREQ 147 mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ 148#endif 149 150 adr r1, _monitor_vectors 151 mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors 152 153 mrc p15, 0, ip, c12, c0, 0 @ save secure copy of VBAR 154 155 isb 156 smc #0 @ call into MONITOR mode 157 158 mcr p15, 0, ip, c12, c0, 0 @ write non-secure copy of VBAR 159 160 mov r1, #1 161 str r1, [r3, #GICC_CTLR] @ enable non-secure CPU i/f 162 add r2, r2, #GIC_DIST_OFFSET 163 str r1, [r2, #GICD_CTLR] @ allow private interrupts 164 165 mov r0, r3 @ return GICC address 166 167 bx lr 168ENDPROC(_nonsec_init) 169 170#ifdef CONFIG_SMP_PEN_ADDR 171/* void __weak smp_waitloop(unsigned previous_address); */ 172ENTRY(smp_waitloop) 173 wfi 174 ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address 175 ldr r1, [r1] 176 cmp r0, r1 @ make sure we dont execute this code 177 beq smp_waitloop @ again (due to a spurious wakeup) 178 mov pc, r1 179ENDPROC(smp_waitloop) 180.weak smp_waitloop 181#endif 182 183ENTRY(_switch_to_hyp) 184 mov r0, lr 185 mov r1, sp @ save SVC copy of LR and SP 186 isb 187 hvc #0 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1 188 mov sp, r1 189 mov lr, r0 @ restore SVC copy of LR and SP 190 191 bx lr 192ENDPROC(_switch_to_hyp) 193