1/* 2 * code for switching cores into non-secure state and into HYP mode 3 * 4 * Copyright (c) 2013 Andre Przywara <andre.przywara@linaro.org> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#include <config.h> 10#include <linux/linkage.h> 11#include <asm/gic.h> 12#include <asm/armv7.h> 13#include <asm/proc-armv/ptrace.h> 14 15.arch_extension sec 16.arch_extension virt 17 18 .pushsection ._secure.text, "ax" 19 20 .align 5 21/* the vector table for secure state and HYP mode */ 22_monitor_vectors: 23 .word 0 /* reset */ 24 .word 0 /* undef */ 25 adr pc, _secure_monitor 26 .word 0 27 .word 0 28 .word 0 29 .word 0 30 .word 0 31 32.macro is_cpu_virt_capable tmp 33 mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1 34 and \tmp, \tmp, #CPUID_ARM_VIRT_MASK @ mask virtualization bits 35 cmp \tmp, #(1 << CPUID_ARM_VIRT_SHIFT) 36.endm 37 38/* 39 * secure monitor handler 40 * U-boot calls this "software interrupt" in start.S 41 * This is executed on a "smc" instruction, we use a "smc #0" to switch 42 * to non-secure state. 43 * r0, r1, r2: passed to the callee 44 * ip: target PC 45 */ 46_secure_monitor: 47#ifdef CONFIG_ARMV7_PSCI 48 ldr r5, =_psci_vectors @ Switch to the next monitor 49 mcr p15, 0, r5, c12, c0, 1 50 isb 51 52 @ Obtain a secure stack, and configure the PSCI backend 53 bl psci_arch_init 54#endif 55 56 mrc p15, 0, r5, c1, c1, 0 @ read SCR 57 bic r5, r5, #0x4a @ clear IRQ, EA, nET bits 58 orr r5, r5, #0x31 @ enable NS, AW, FW bits 59 @ FIQ preserved for secure mode 60 mov r6, #SVC_MODE @ default mode is SVC 61 is_cpu_virt_capable r4 62#ifdef CONFIG_ARMV7_VIRT 63 orreq r5, r5, #0x100 @ allow HVC instruction 64 moveq r6, #HYP_MODE @ Enter the kernel as HYP 65#endif 66 67 mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set) 68 isb 69 70 bne 1f 71 72 @ Reset CNTVOFF to 0 before leaving monitor mode 73 mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1 74 ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits 75 movne r4, #0 76 mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero 771: 78 mov lr, ip 79 mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F 80 tst lr, #1 @ Check for Thumb PC 81 orrne ip, ip, #T_BIT @ Set T if Thumb 82 orr ip, ip, r6 @ Slot target mode in 83 msr spsr_cxfs, ip @ Set full SPSR 84 movs pc, lr @ ERET to non-secure 85 86ENTRY(_do_nonsec_entry) 87 mov ip, r0 88 mov r0, r1 89 mov r1, r2 90 mov r2, r3 91 smc #0 92ENDPROC(_do_nonsec_entry) 93 94.macro get_cbar_addr addr 95#ifdef CONFIG_ARM_GIC_BASE_ADDRESS 96 ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS 97#else 98 mrc p15, 4, \addr, c15, c0, 0 @ read CBAR 99 bfc \addr, #0, #15 @ clear reserved bits 100#endif 101.endm 102 103.macro get_gicd_addr addr 104 get_cbar_addr \addr 105 add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset 106.endm 107 108.macro get_gicc_addr addr, tmp 109 get_cbar_addr \addr 110 is_cpu_virt_capable \tmp 111 movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9 112 moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7 113 add \addr, \addr, \tmp 114.endm 115 116#ifndef CONFIG_ARMV7_PSCI 117/* 118 * Secondary CPUs start here and call the code for the core specific parts 119 * of the non-secure and HYP mode transition. The GIC distributor specific 120 * code has already been executed by a C function before. 121 * Then they go back to wfi and wait to be woken up by the kernel again. 122 */ 123ENTRY(_smp_pen) 124 cpsid i 125 cpsid f 126 127 bl _nonsec_init 128 129 adr r0, _smp_pen @ do not use this address again 130 b smp_waitloop @ wait for IPIs, board specific 131ENDPROC(_smp_pen) 132#endif 133 134/* 135 * Switch a core to non-secure state. 136 * 137 * 1. initialize the GIC per-core interface 138 * 2. allow coprocessor access in non-secure modes 139 * 140 * Called from smp_pen by secondary cores and directly by the BSP. 141 * Do not assume that the stack is available and only use registers 142 * r0-r3 and r12. 143 * 144 * PERIPHBASE is used to get the GIC address. This could be 40 bits long, 145 * though, but we check this in C before calling this function. 146 */ 147ENTRY(_nonsec_init) 148 get_gicd_addr r3 149 150 mvn r1, #0 @ all bits to 1 151 str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts 152 153 get_gicc_addr r3, r1 154 155 mov r1, #3 @ Enable both groups 156 str r1, [r3, #GICC_CTLR] @ and clear all other bits 157 mov r1, #0xff 158 str r1, [r3, #GICC_PMR] @ set priority mask register 159 160 mrc p15, 0, r0, c1, c1, 2 161 movw r1, #0x3fff 162 movt r1, #0x0004 163 orr r0, r0, r1 164 mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec 165 166/* The CNTFRQ register of the generic timer needs to be 167 * programmed in secure state. Some primary bootloaders / firmware 168 * omit this, so if the frequency is provided in the configuration, 169 * we do this here instead. 170 * But first check if we have the generic timer. 171 */ 172#ifdef CONFIG_TIMER_CLK_FREQ 173 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 174 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits 175 cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT) 176 ldreq r1, =CONFIG_TIMER_CLK_FREQ 177 mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ 178#endif 179 180 adr r1, _monitor_vectors 181 mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors 182 isb 183 184 mov r0, r3 @ return GICC address 185 bx lr 186ENDPROC(_nonsec_init) 187 188#ifdef CONFIG_SMP_PEN_ADDR 189/* void __weak smp_waitloop(unsigned previous_address); */ 190ENTRY(smp_waitloop) 191 wfi 192 ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address 193 ldr r1, [r1] 194#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN 195 rev r1, r1 196#endif 197 cmp r0, r1 @ make sure we dont execute this code 198 beq smp_waitloop @ again (due to a spurious wakeup) 199 mov r0, r1 200 b _do_nonsec_entry 201ENDPROC(smp_waitloop) 202.weak smp_waitloop 203#endif 204 205 .popsection 206