1/* 2 * code for switching cores into non-secure state and into HYP mode 3 * 4 * Copyright (c) 2013 Andre Przywara <andre.przywara@linaro.org> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#include <config.h> 10#include <linux/linkage.h> 11#include <asm/gic.h> 12#include <asm/armv7.h> 13#include <asm/proc-armv/ptrace.h> 14 15.arch_extension sec 16.arch_extension virt 17 18 .pushsection ._secure.text, "ax" 19 20 .align 5 21/* the vector table for secure state and HYP mode */ 22_monitor_vectors: 23 .word 0 /* reset */ 24 .word 0 /* undef */ 25 adr pc, _secure_monitor 26 .word 0 27 .word 0 28 .word 0 29 .word 0 30 .word 0 31 32.macro is_cpu_virt_capable tmp 33 mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1 34 and \tmp, \tmp, #CPUID_ARM_VIRT_MASK @ mask virtualization bits 35 cmp \tmp, #(1 << CPUID_ARM_VIRT_SHIFT) 36.endm 37 38/* 39 * secure monitor handler 40 * U-Boot calls this "software interrupt" in start.S 41 * This is executed on a "smc" instruction, we use a "smc #0" to switch 42 * to non-secure state. 43 * r0, r1, r2: passed to the callee 44 * ip: target PC 45 */ 46_secure_monitor: 47#ifdef CONFIG_ARMV7_PSCI 48 ldr r5, =_psci_vectors @ Switch to the next monitor 49 mcr p15, 0, r5, c12, c0, 1 50 isb 51 52 @ Obtain a secure stack, and configure the PSCI backend 53 bl psci_arch_init 54#endif 55 56#ifdef CONFIG_ARM_ERRATA_773022 57 mrc p15, 0, r5, c1, c0, 1 58 orr r5, r5, #(1 << 1) 59 mcr p15, 0, r5, c1, c0, 1 60 isb 61#endif 62 63#ifdef CONFIG_ARM_ERRATA_774769 64 mrc p15, 0, r5, c1, c0, 1 65 orr r5, r5, #(1 << 25) 66 mcr p15, 0, r5, c1, c0, 1 67 isb 68#endif 69 70 mrc p15, 0, r5, c1, c1, 0 @ read SCR 71 bic r5, r5, #0x4a @ clear IRQ, EA, nET bits 72 orr r5, r5, #0x31 @ enable NS, AW, FW bits 73 @ FIQ preserved for secure mode 74 mov r6, #SVC_MODE @ default mode is SVC 75 is_cpu_virt_capable r4 76#ifdef CONFIG_ARMV7_VIRT 77 orreq r5, r5, #0x100 @ allow HVC instruction 78 moveq r6, #HYP_MODE @ Enter the kernel as HYP 79#endif 80 81 mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set) 82 isb 83 84 bne 1f 85 86 @ Reset CNTVOFF to 0 before leaving monitor mode 87 mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1 88 ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits 89 movne r4, #0 90 mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero 911: 92 mov lr, ip 93 mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F 94 tst lr, #1 @ Check for Thumb PC 95 orrne ip, ip, #T_BIT @ Set T if Thumb 96 orr ip, ip, r6 @ Slot target mode in 97 msr spsr_cxfs, ip @ Set full SPSR 98 movs pc, lr @ ERET to non-secure 99 100ENTRY(_do_nonsec_entry) 101 mov ip, r0 102 mov r0, r1 103 mov r1, r2 104 mov r2, r3 105 smc #0 106ENDPROC(_do_nonsec_entry) 107 108.macro get_cbar_addr addr 109#ifdef CONFIG_ARM_GIC_BASE_ADDRESS 110 ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS 111#else 112 mrc p15, 4, \addr, c15, c0, 0 @ read CBAR 113 bfc \addr, #0, #15 @ clear reserved bits 114#endif 115.endm 116 117.macro get_gicd_addr addr 118 get_cbar_addr \addr 119 add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset 120.endm 121 122.macro get_gicc_addr addr, tmp 123 get_cbar_addr \addr 124 is_cpu_virt_capable \tmp 125 movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9 126 moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7 127 add \addr, \addr, \tmp 128.endm 129 130#ifndef CONFIG_ARMV7_PSCI 131/* 132 * Secondary CPUs start here and call the code for the core specific parts 133 * of the non-secure and HYP mode transition. The GIC distributor specific 134 * code has already been executed by a C function before. 135 * Then they go back to wfi and wait to be woken up by the kernel again. 136 */ 137ENTRY(_smp_pen) 138 cpsid i 139 cpsid f 140 141 bl _nonsec_init 142 143 adr r0, _smp_pen @ do not use this address again 144 b smp_waitloop @ wait for IPIs, board specific 145ENDPROC(_smp_pen) 146#endif 147 148/* 149 * Switch a core to non-secure state. 150 * 151 * 1. initialize the GIC per-core interface 152 * 2. allow coprocessor access in non-secure modes 153 * 154 * Called from smp_pen by secondary cores and directly by the BSP. 155 * Do not assume that the stack is available and only use registers 156 * r0-r3 and r12. 157 * 158 * PERIPHBASE is used to get the GIC address. This could be 40 bits long, 159 * though, but we check this in C before calling this function. 160 */ 161ENTRY(_nonsec_init) 162 get_gicd_addr r3 163 164 mvn r1, #0 @ all bits to 1 165 str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts 166 167 get_gicc_addr r3, r1 168 169 mov r1, #3 @ Enable both groups 170 str r1, [r3, #GICC_CTLR] @ and clear all other bits 171 mov r1, #0xff 172 str r1, [r3, #GICC_PMR] @ set priority mask register 173 174 mrc p15, 0, r0, c1, c1, 2 175 movw r1, #0x3fff 176 movt r1, #0x0004 177 orr r0, r0, r1 178 mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec 179 180/* The CNTFRQ register of the generic timer needs to be 181 * programmed in secure state. Some primary bootloaders / firmware 182 * omit this, so if the frequency is provided in the configuration, 183 * we do this here instead. 184 * But first check if we have the generic timer. 185 */ 186#ifdef CONFIG_TIMER_CLK_FREQ 187 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 188 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits 189 cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT) 190 ldreq r1, =CONFIG_TIMER_CLK_FREQ 191 mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ 192#endif 193 194 adr r1, _monitor_vectors 195 mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors 196 isb 197 198 mov r0, r3 @ return GICC address 199 bx lr 200ENDPROC(_nonsec_init) 201 202#ifdef CONFIG_SMP_PEN_ADDR 203/* void __weak smp_waitloop(unsigned previous_address); */ 204ENTRY(smp_waitloop) 205 wfi 206 ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address 207 ldr r1, [r1] 208#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN 209 rev r1, r1 210#endif 211 cmp r0, r1 @ make sure we dont execute this code 212 beq smp_waitloop @ again (due to a spurious wakeup) 213 mov r0, r1 214 b _do_nonsec_entry 215ENDPROC(smp_waitloop) 216.weak smp_waitloop 217#endif 218 219 .popsection 220