1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2015 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <asm/arch/clock.h> 8 #include <asm/io.h> 9 #include <asm/arch/fsl_serdes.h> 10 #include <asm/arch/immap_ls102xa.h> 11 #include <asm/arch/ls102xa_soc.h> 12 #include <asm/arch/ls102xa_stream_id.h> 13 #include <fsl_csu.h> 14 #include <fsl_ddr_sdram.h> 15 16 struct liodn_id_table sec_liodn_tbl[] = { 17 SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10), 18 SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10), 19 SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10), 20 SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10), 21 SET_SEC_RTIC_LIODN_ENTRY(a, 0x10), 22 SET_SEC_RTIC_LIODN_ENTRY(b, 0x10), 23 SET_SEC_RTIC_LIODN_ENTRY(c, 0x10), 24 SET_SEC_RTIC_LIODN_ENTRY(d, 0x10), 25 SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10), 26 SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10), 27 SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10), 28 SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10), 29 SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10), 30 SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10), 31 SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10), 32 SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10), 33 }; 34 35 struct smmu_stream_id dev_stream_id[] = { 36 { 0x100, 0x01, "ETSEC MAC1" }, 37 { 0x104, 0x02, "ETSEC MAC2" }, 38 { 0x108, 0x03, "ETSEC MAC3" }, 39 { 0x10c, 0x04, "PEX1" }, 40 { 0x110, 0x05, "PEX2" }, 41 { 0x114, 0x06, "qDMA" }, 42 { 0x118, 0x07, "SATA" }, 43 { 0x11c, 0x08, "USB3" }, 44 { 0x120, 0x09, "QE" }, 45 { 0x124, 0x0a, "eSDHC" }, 46 { 0x128, 0x0b, "eMA" }, 47 { 0x14c, 0x0c, "2D-ACE" }, 48 { 0x150, 0x0d, "USB2" }, 49 { 0x18c, 0x0e, "DEBUG" }, 50 }; 51 52 unsigned int get_soc_major_rev(void) 53 { 54 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 55 unsigned int svr, major; 56 57 svr = in_be32(&gur->svr); 58 major = SVR_MAJ(svr); 59 60 return major; 61 } 62 63 static void erratum_a009008(void) 64 { 65 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008 66 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 67 68 clrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4, 69 0xF << 6, 70 SCFG_USB_TXVREFTUNE << 6); 71 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ 72 } 73 74 static void erratum_a009798(void) 75 { 76 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798 77 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 78 79 clrbits_be32(scfg + SCFG_USB3PRM1CR / 4, 80 SCFG_USB_SQRXTUNE_MASK << 23); 81 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ 82 } 83 84 static void erratum_a008997(void) 85 { 86 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997 87 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; 88 89 clrsetbits_be32(scfg + SCFG_USB3PRM2CR / 4, 90 SCFG_USB_PCSTXSWINGFULL_MASK, 91 SCFG_USB_PCSTXSWINGFULL_VAL); 92 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ 93 } 94 95 static void erratum_a009007(void) 96 { 97 #ifdef CONFIG_SYS_FSL_ERRATUM_A009007 98 void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE; 99 100 out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); 101 out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); 102 out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); 103 out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4); 104 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ 105 } 106 107 static void erratum_a008850_early(void) 108 { 109 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 110 /* part 1 of 2 */ 111 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + 112 CONFIG_SYS_CCI400_OFFSET); 113 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 114 115 /* disables propagation of barrier transactions to DDRC from CCI400 */ 116 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); 117 118 /* disable the re-ordering in DDRC */ 119 out_be32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 120 #endif 121 } 122 123 void erratum_a008850_post(void) 124 { 125 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850 126 /* part 2 of 2 */ 127 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + 128 CONFIG_SYS_CCI400_OFFSET); 129 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; 130 u32 tmp; 131 132 /* enable propagation of barrier transactions to DDRC from CCI400 */ 133 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); 134 135 /* enable the re-ordering in DDRC */ 136 tmp = in_be32(&ddr->eor); 137 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); 138 out_be32(&ddr->eor, tmp); 139 #endif 140 } 141 142 void s_init(void) 143 { 144 } 145 146 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 147 void erratum_a010315(void) 148 { 149 int i; 150 151 for (i = PCIE1; i <= PCIE2; i++) 152 if (!is_serdes_configured(i)) { 153 debug("PCIe%d: disabled all R/W permission!\n", i); 154 set_pcie_ns_access(i, 0); 155 } 156 } 157 #endif 158 159 int arch_soc_init(void) 160 { 161 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; 162 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + 163 CONFIG_SYS_CCI400_OFFSET); 164 unsigned int major; 165 166 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS 167 enable_layerscape_ns_access(); 168 #endif 169 170 #ifdef CONFIG_FSL_QSPI 171 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); 172 #endif 173 174 #ifdef CONFIG_VIDEO_FSL_DCU_FB 175 out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); 176 #endif 177 178 /* Configure Little endian for SAI, ASRC and SPDIF */ 179 out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE); 180 181 /* 182 * Enable snoop requests and DVM message requests for 183 * All the slave insterfaces. 184 */ 185 out_le32(&cci->slave[0].snoop_ctrl, 186 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 187 out_le32(&cci->slave[1].snoop_ctrl, 188 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 189 out_le32(&cci->slave[2].snoop_ctrl, 190 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 191 out_le32(&cci->slave[4].snoop_ctrl, 192 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); 193 194 major = get_soc_major_rev(); 195 if (major == SOC_MAJOR_VER_1_0) { 196 /* 197 * Set CCI-400 Slave interface S1, S2 Shareable Override 198 * Register All transactions are treated as non-shareable 199 */ 200 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 201 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); 202 } 203 204 /* Enable all the snoop signal for various masters */ 205 out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR | 206 SCFG_SNPCNFGCR_DCU_RD_WR | 207 SCFG_SNPCNFGCR_SATA_RD_WR | 208 SCFG_SNPCNFGCR_USB3_RD_WR | 209 SCFG_SNPCNFGCR_DBG_RD_WR | 210 SCFG_SNPCNFGCR_EDMA_SNP); 211 212 /* 213 * Memory controller require a register write before being enabled. 214 * Affects: DDR 215 * Register: EDDRTQCFG 216 * Description: Memory controller performance is not optimal with 217 * default internal target queue register values. 218 * Workaround: Write a value of 63b2_0042h to address: 157_020Ch. 219 */ 220 out_be32(&scfg->eddrtqcfg, 0x63b20042); 221 222 /* Erratum */ 223 erratum_a008850_early(); 224 erratum_a009008(); 225 erratum_a009798(); 226 erratum_a008997(); 227 erratum_a009007(); 228 229 return 0; 230 } 231 232 int ls102xa_smmu_stream_id_init(void) 233 { 234 ls1021x_config_caam_stream_id(sec_liodn_tbl, 235 ARRAY_SIZE(sec_liodn_tbl)); 236 237 ls102xa_config_smmu_stream_id(dev_stream_id, 238 ARRAY_SIZE(dev_stream_id)); 239 240 return 0; 241 } 242