1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/arch/fsl_serdes.h> 9 #include <asm/arch/immap_ls102xa.h> 10 11 static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = { 12 [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1}, 13 [0x10] = {PCIE1, SATA1, PCIE2, PCIE2}, 14 [0x20] = {PCIE1, SGMII_TSEC1, PCIE2, SGMII_TSEC2}, 15 [0x30] = {PCIE1, SATA1, SGMII_TSEC1, SGMII_TSEC2}, 16 [0x40] = {PCIE1, PCIE1, SATA1, SGMII_TSEC2}, 17 [0x50] = {PCIE1, PCIE1, PCIE2, SGMII_TSEC2}, 18 [0x60] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2}, 19 [0x70] = {PCIE1, SATA1, PCIE2, SGMII_TSEC2}, 20 [0x80] = {PCIE2, PCIE2, PCIE2, PCIE2}, 21 }; 22 23 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) 24 { 25 return serdes_cfg_tbl[cfg][lane]; 26 } 27 28 int is_serdes_prtcl_valid(int serdes, u32 prtcl) 29 { 30 int i; 31 32 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) 33 return 0; 34 35 for (i = 0; i < SRDS_MAX_LANES; i++) { 36 if (serdes_cfg_tbl[prtcl][i] != NONE) 37 return 1; 38 } 39 40 return 0; 41 } 42